Active filter circuit with dynamically modifiable internal gain

ABSTRACT

Techniques are provided for the implementation of a signal processing circuit ( 100 ) which expands the dynamic range of the signal processing circuit ( 100 ) without interrupting the output of the circuit. The techniques can receive an input signal ( 104 ), process the signal ( 104 ) through one of a plurality of dynamically modifiable signal processing circuits, and switch ( 130 ) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.

SPECIFICATION

[0001] This application claims priority to U.S. Provisional ApplicationSerial No. 60/260,722 filed Jan. 10, 2001, and U.S. ProvisionalApplication Serial No. 60/288,976 filed May 4, 2001, each of which isincorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to signal processors and, moreparticularly, to signal processors that are dynamically modifiable foroptimal performance and reduced power dissipation.

[0003] In order to expand the dynamic range of a signal processingsystem, companding signal processors can be used. A companding signalprocessor uses an input amplifier to amplify or attenuate a signalbefore it is provided to a signal processor, and an output amplifier isused to amplify or attenuate the signal provided by the signalprocessor. A signal processing circuit or signal processor includes anactive filter. The gain of the output amplifier is the inverse of thegain of the input amplifier, thus conserving the overall gain of thesignal processor. Ideally, the gains of the input amplifier and outputamplifier should be dynamically variable. A signal strength detector canbe used to measure the strength of the input signal and provide aprocessor appropriate gain control signal to the input amplifier and theoutput amplifier. See Y. Tsividis, “Externally linear, time-invariantsystems and their application to companding signal processors,” IEEETransactions on Circuits and Systems II, Vol. 44, No. 2, February 1997.The gain control signal sets the amplification factors of the inputamplifier and the output amplifier. However, this approach has theproblem in that because the signal processor has memory, distortion inthe output of the signal processor occurs whenever the amplificationfactors of the input amplifier and the output amplifier are changed.

[0004] The analog floating point technique addresses the problem ofdistortion in the output whenever the amplification factors change. SeeE. Blumenkrantz, “The analog floating point technique,” Proc. IEEESymposium on Low Power Electronics, p. 72-73, 1995. This techniqueavoids distortion by altering the state variables of the signalprocessor when the amplification factors change. However, implementationof the analog floating point technique is complicated, and is sensitiveto parasitics and component mismatch. Accordingly, there is a need forcircuits which expand the dynamic range of a signal processor withoutinterrupting the output of the system or causing distortion.

SUMMARY OF THE INVENTION

[0005] It is therefore an object of this invention to provide a circuitwhich has a large dynamic range and which operates in anenergy-efficient manner without interrupting the output of the circuitor causing distortion.

[0006] In accordance with the present invention, there is provided anactive filter system including a system input for receiving a systeminput signal, a system output for providing a system output signal, amain filter, a strength detector, a zero crossing detector and a gaincontrol unit. The main filter having at least one successive filterstage having an input and an output, including a first filter stage,each filter stage having an associated input amplification stageincluding a signal input, a signal output coupled to the input of theassociated filter stage and a gain control input for receiving a gaincontrol signal that determines the amplification factor of theassociated input amplification stage, the input of the inputamplification stage associated with each filter stage, except for theinput amplification stage associated with the first filter stage, beingcoupled to the output of a preceding filter stage, if any, the input ofthe amplification stage associated with the first filter stage beingcoupled to the system input, each filter stage having an associatedoutput amplification stage including a signal input coupled to theoutput of the associated filter stage, a signal output and a gaincontrol input for receiving a gain control signal that determines theamplification factor of the associated output amplification stage, thesignal output of the output amplification stage associated with aselected one of the at least one filter stage being coupled to thesystem output. The strength detector having an input coupled to theoutput of the first filter stage, and having a first output and a secondoutput for providing respective output signals indicative of whether thefirst filter stage is approaching saturation or is providing an outputsignal having less than a minimum acceptable signal to noise ratio. Thezero crossing detector having at least one input coupled to respectiveones of the at least one output of the at least one filter stage of themain filter, and having at least one output for providing at least onesignal indicative of when a successive one of the at least one filterstage of the main filter provides a signal at its output that isapproximately equal to zero. The gain control unit having a first inputand a second input respectively coupled to the output of the strengthdetector and coupled to the at least one output of the zero crossingdetector, and having a multiplicity of outputs for providing respectivegain control signals to the gain control input of each inputamplification stage and each output amplification stage associated withthe at least one filter stage of the main filter, the gain control unitbeing responsive to signals provided initially by the strength detectorindicative of the first filter stage approaching saturation or providingan output signal having less than the minimum acceptable signal to noiseratio, and a signal from the zero crossing detector indicative of theoutput signal provided by the first filter stage being approximatelyequal to zero for providing a gain control signal to the gain controlinput of the input amplification stage associated with the first filterstage so that the input amplification stage associated with the firstfilter stage has an amplification factor that results in a signalstrength at its signal output which avoids saturation of the firstfilter stage and avoids the first filter stage providing a signal havingless than the minimum acceptable signal to noise ratio, and forproviding a gain control signal to the gain control input of the outputamplification stage associated with the first filter stage so that theoutput amplification stage associated with the first filter stage has anamplification factor which is the reciprocal of the amplification factorof the input amplification stage associated with the first filter stage,the gain control unit being thereafter responsive to signals providedinitially by the strength detector indicative of the first filter stageof the main filter approaching saturation or providing an output havingless than the minimum acceptable signal to noise ratio, and to a signalfrom the zero crossing detector indicating that an output signal at theoutput of a successive filter stage, if any, being approximately equalto zero for providing a gain control signal to the gain control input ofthe input amplification stage associated with the successive filterstage so that the input amplification stage associated with thesuccessive filter stage has an amplification factor that results in asignal strength at its signal output that avoids saturation of thesuccessive filter stage and avoids the successive filter stage providinga signal having less than the minimum acceptable signal to noise ratio,and for providing a gain control signal to the gain control input of theoutput amplification stage associated with the successive filter stageso that the output amplification stage associated with the successivefilter stage has an amplification factor which is a reciprocal of theamplification factor of the input amplification stage associated withthe successive filter stage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Further objects, features, and advantages of the invention willbecome apparent from the following detailed description taken inconjunction with the accompanying figures showing illustrativeembodiments of the invention, in which:

[0008]FIG. 1 is a block diagram illustrating a prior art signalprocessing system;

[0009]FIG. 2 is a block diagram illustrating a signal processing systemin accordance with the present invention;

[0010]FIG. 3 is a circuit diagram illustrating the main filter of asignal processing system in accordance with the present invention;

[0011]FIG. 4 is a circuit diagram illustrating a switching unit of asignal processing system in accordance with the present invention;

[0012]FIG. 5 is a circuit diagram illustrating a shift register usablein a signal processing system in accordance with the present invention;

[0013]FIG. 6 is a circuit diagram illustrating a strength detector of asignal processing system in accordance with the present invention;

[0014]FIG. 7 is a circuit diagram illustrating a peak detector of asignal processing system in accordance with the present invention;

[0015]FIG. 8 is a circuit diagram illustrating a threshold detector of asignal processing system in accordance with the present invention;

[0016] FIGS. 9(a) and 9(b) are circuit diagrams illustrating a gaincontrol unit of a signal processing system in accordance with thepresent invention;

[0017]FIG. 10 is a circuit diagram illustrating a comparator of a signalprocessing system in accordance with the present invention; and

[0018]FIG. 11 is a circuit diagram illustrating a transconductor of asignal processing system in accordance with the present invention.

[0019] Throughout the figures, unless otherwise stated, the samereference numerals and characters are used to denote like features,elements, components, or portions of the illustrated embodiments.Moreover, while the subject invention will now be described in detailwith reference to the figures, and in connection with the illustrativeembodiments, various changes and modifications to the describedembodiments will be apparent to those skilled in the art withoutdeparting from the true scope and spirit of the subject invention asdefined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0020]FIG. 1 illustrates an example of a prior art signal processingsystem 10. The signal processing system 10 is a companding filter. Acompanding filter amplifies or attenuates an input signal that isapplied to a filter circuit, and attenuates or amplifies the outputsignal from the circuit. The prior art companding filter 10 includes aninput 12, a signal strength detector 14, an input variable gainamplifier 16, a main filter 18, an output variable gain amplifier 20,and an output 22.

[0021] The input 12 of the signal processing system 10 is coupled toinput 11 of the signal strength detector 14 and an input 30 of avariable gain input amplifier 16. The variable gain input amplifier 16amplifies or attenuates the signal received by the input 30 depending ona gain control input signal received at a gain control input 13 of thevariable gain input amplifier 16 and provides the resulting signal atits output 15. The output 15 of the variable gain input amplifier 16 iscoupled to input 17 of a main filter 18. The main filter 18 processesthe signal received at its input 17 and produces a processed outputsignal at its output 19. The output 19 of the main filter 18 is coupledto input 21 of a variable gain output amplifier 20. The variable gainoutput amplifier 20 amplifies or attenuates the signal received at itsinput 21 depending on a gain control signal received at a gain controlinput 23 of the variable gain output amplifier 20 and provides aresulting signal at its output 24. The gain of the variable gain outputamplifier 20 is the inverse of the gain of the variable gain inputamplifier 16. The output 24 of the variable gain output amplifier 20 isconnected to the output 22 of the signal processing system 10.

[0022] The signal strength detector 14 measures the strength (e.g., thevoltage envelope) of the signal applied to the input 11 of the signalstrength detector 14 and provides a gain control signal at its output25, which is connected to the gain control inputs 13 and 23 of thevariable gain input amplifier 16 and the variable gain output amplifier20, respectively. Depending on the strength of the signal at the input11 of the signal strength detector 14, different gain control signalsare provided at the output 25 of the signal strength detector 14. If thesignal applied to the input 12 of the signal processing system 10 issmall, the strength detector 11 provides a gain control signal thatcauses the variable gain input amplifier 16 to have a relatively highgain, thereby causing the signal applied to the input 12 of the signalprocessing system 10 to be amplified before it is applied to the mainfilter 18, such that the signal is above the noise floor of the filter18, i.e., the noise generated by the filter. If the signal applied tothe input 12 of the signal processing system 10, the strength deflector14 provides a gain control signal that causes the variable gain inputamplifier 16 to have a relatively low gain, thereby causing the signalapplied to the input 12 of the signal processing system 10 to beslightly amplified or even attenuated before it is applied to the mainfilter 18 to avoid saturating the main filter 18.

[0023]FIG. 2 illustrates an exemplary signal processing system 100 inaccordance with the present invention. The signal processing system 100generates a processed signal with a strong in channel component wellabove the filter noise. The signal processing system 100 includes asystem input 102, a main filter 106, a switching unit 130, a comparator136, a shift register 144, a strength detector 154, a gain control unit172, and a system output 190.

[0024] A signal received by the system input 102 of the signalprocessing system 100, which typically includes an in-band component andan out-band component, is applied to an input 104 of the main filter106. In the present embodiment, the main filter 106 is a second orderfilter, which includes two integrators (not shown in FIG. 2).Preferably, the main filter 106 has enough linear range to accommodatethe in-band component and the out-band component of the signal withoutsaturating. Each of the first and second integrators has a variableinput gain stage and a variable output gain stage associated with it(not shown in FIG. 2). The main filter 106 processes the signal receivedat its input 104 as controlled by respective signals received at inputs108, 110, 112, 114 and 116. These signals control the gain of thevariable input gain stage and the variable output gain stage for each ofthe first and second integrators. The gain of the variable input gainstage and variable output gain stages associated with the firstintegrator should only be changed when the output of the firstintegrator is at or near zero. By changing the gain of the variableinput gain stage and the variable output gain stage associated with thefirst integrator when the output of the first integrator is at or nearzero, little or no transients are created in the signal produced at theoutput of the first integrator. Likewise, the gain of the variable inputgain stage and the variable output gain stage associated with the secondintegrator should only be changed when the output of the secondintegrator is at or near zero. The main filter 106 produces a processedsignal at each of its outputs 118, 120 and 122. The signal produced atthe output 118 of the main filter 106 is the output of the firstintegrator of the main filter 106. The output 118 of the main filter 106is connected to an input 124 of the switching unit 130, and an input 152of the strength detector 154. The signal produced at the output 120 ofthe main filter 106 is the output of the second integrator of the mainfilter 106. The output 120 of the main filter 106 is connected toanother input 126 of the switching unit 130. The signal produced at theoutput 122 of the main filter 106 is the output of the variable gainoutput stage associated with the first integrator of the main filter106. The output 122 of the main filter 106 is connected to the systemoutput 190 of the signal processing system 100. The structure andoperation of the main filter 106 is described in greater detailhereinbelow with reference to FIG. 3.

[0025] The switching unit 130 applies one of the signals received at itsinputs 124, 126 to its output 132 in response to a signal received at aninput 128. If a logical one voltage level (i.e., 5 V) is received at theinput 128, the switching unit 130 connects the input 124 and the output132, and disconnects the input 120 from the output 132. If a logicalzero voltage level (i.e., ground potential) is received at the input128, the switching unit 130 connects the input 126 to the output 132 anddisconnects the input 124 from the output 132. The output 132 isconnected to an input 134 of the comparator 136.

[0026] The comparator 136 compares a signal received at the input 134against a reference voltage. If the voltage of the signal received atthe input 134 is approximately equal to the reference voltage, thecomparator 136 produces a signal equal to a logical one voltage level atan output 138 of the comparator 136. If the voltage of the signalreceived at the input 134 is not approximately equal to the referencevoltage, the comparator 136 produces a signal equal to a logical zerovoltage level at the output 138 of the comparator 136. The output 138 ofthe comparator 136 is connected to a clock input 140 of the shiftregister 144. In the present embodiment, the reference voltage may bezero.

[0027] The shift register 144 determines which of the outputs of theintegrators of the main filter 106 the comparator 136 should measureagainst the reference voltage. A reset/enable input 142 of the shiftregister 144 is connected to an output 176 of the gain control unit 172.Outputs 146, 148, 150 of the shift register 144 are connected to inputs166, 168, 170, respectively, of the gain control unit 172. If a logicalone voltage level is received at the reset/enable input 142, the shiftregister 144 provides a logical one voltage level signal at the output146, a logical zero voltage level signal at the output 148 and a logicalzero voltage level signal at the output 150. If a logical zero voltagelevel signal is received at the reset/enable input 142 and a positiveedge (i.e., a logical zero voltage level changing to a logical onevoltage level) is received at the input 140, the shift register 144produces a logical zero voltage level signal on the output 146, producesa signal on the output 148 equal to the signal formerly on the output146, and produces a signal on the output 150 equal to a logical OR ofthe signal formerly on the output 148 and the signal formerly on theoutput 150. The structure and operation of the shift register will bedescribed in greater detail hereinbelow with reference to FIG. 5.

[0028] The signal strength detector 154 selects an amplification factorthat is the most suitable for processing the signal received by thesystem input 102 of the signal processing system 100. The input 152 ofthe signal strength detector 154 is connected to the output 118 of themain filter 106, and outputs 156 and 158 of the signal strength detector154 are connected to inputs 160 and 162, respectively, of the gaincontrol unit 164. The signal strength detector 154 detects the voltageenvelope of a signal received at the input 152 of the signal strengthdetector 154. A combination of a rectifier and a low-pass filter,well-known for use in many other applications, is one example of acircuit which can be used as an envelope detector of the signal strengthdetector 154. The signal strength detector 154 determines if the voltageenvelope of the signal provided by the output 118 of the main filter 106is below a first threshold whereby the signal to noise ratio of theoutput signal of the main filter 106 is approaching a minimum tolerablevalue with the main filter 106 having the present amplification factors,or exceeds a second threshold whereby the main filter 106 is enteringsaturation with the present amplification factors.

[0029] If the signal strength detector 154 detects that the voltageenvelope of the signal received at its input 152 is not below the firstthreshold or does not exceed the second threshold, the signal strengthdetector 154 produces a signal equal to a logical zero voltage level onthe output 156, and a signal equal to a logical zero voltage level onthe output 158. For purposes of the specification and claims, positivelogic is assumed. If the signal strength detector 154 detects that thevoltage envelope of the signal received at its input 152 falls below thefirst threshold and does not exceed the second threshold, the signalstrength detector 154 produces a logical one voltage level signal on itsoutput 158, and a logical zero voltage level signal on its output 156.If the signal strength detector 154 detects that the voltage envelope ofthe signal received at its input 152 exceeds the first threshold andexceeds the second threshold, the signal strength detector produces alogical zero voltage level signal on its output 158, and a logical onevoltage level signal on its output 156.

[0030] The gain control unit 172, responsive to signals received at itsinputs 160, 162, 166, 168, 170, provides signals at its output 176 tocontrol the preset/enable input 142 of the shift register 144, andprovides signals at its outputs 178, 180, 182, 184, 186 to control therespective amplification factors of the variable gain input stageassociated with the first integrator, the variable gain output stageassociated with the first integrator, the variable gain input stageassociated with the second integrator, and the variable gain outputstage associated with the second integrator. The outputs 178, 180, 182,184, 186 of the gain control unit 172 are connected to the inputs 108,110, 112, 114, 116, respectively, of the main filter 106. The output 176of the gain control unit 172 is connected to the preset/enable input 142of the shift register 144.

[0031] The gain control unit 172 provides signals to the main filter 106and the shift register 144 that allow the amplification factors of theamplifiers within the main filter 106 to vary without causing transientsto appear on signals at the system output 190 of the signal processingsystem 100. The gain control unit 172 begins the process of changing theamplification factors of the amplifiers of the main filter 106 byproviding the preset/enable input 142 of the shift register 144 with alogical one voltage level signal to enable the shift register, which inturn provides a logical one voltage level signal to the input 128 of theswitching unit 130. Once the comparator 136 senses that the signalreceived at the input 124 is equal to the reference voltage, the shiftregister 144 shifts the signals at its outputs 146, 148, 150, and causesa logical zero voltage level signal to be provided to the input 128 ofthe switching unit. This causes the gain control unit 172 to provide themain filter 106 with appropriate signals on its inputs 108, 110, 112,114 to change the amplification factors of the variable gain input stageand the variable gain output stage associated with the first integrator,and the variable gain input stage associated with the second integratorof main filter 106 to the desired values. The amplification factor ofthe variable gain input stage associated with the second integrator mustbe changed at this point to compensate for the amplification factorchange of the variable gain input stage associated with the firstintegrator. Then, once the comparator 136 senses that the signalreceived at the input 124 is equal to the reference voltage again, theshift register 144 shifts the signals at its outputs 146, 148, 150,causing the gain control unit 172 to provide the main filter 106 withthe appropriate signals on its inputs 112, 114, 116 to change theamplification factors of the variable gain input stage and the variablegain output stage associated with the second integrator.

[0032]FIG. 3 illustrates the main filter 106 as shown in FIG. 2. Themain filter 106 is a second order filter, and includes two integrators,a first integrator and a second integrator. Each of the integrators isassociated with a respective variable gain input stage and a respectivevariable gain output stage. The variable gain input stage associatedwith the first integrator consists of resistors 216, 210, 204, 252,switches 232, 224, a capacitor 246, and an operational amplifier 240.The first integrator consists of the operational amplifier 240, thecapacitor 246 and the resistor 252. The variable gain output stageassociated with the first integrator consists of an operationalamplifier 376, resistors 360, 384, 390, 205, and switches 213, 398. Thevariable gain input stage associated with the second integrator consistsof resistors 258, 264, 278, switches 272, 286, a capacitor 334, and anoperational amplifier 328. The second integrator consists of theoperational amplifier 328, and the capacitor 334. The variable gainoutput amplification stage associated with the second integratorincludes resistors 252, 292, 298, 312, 340, 354, switches 306, 320,operational amplifiers 240, 348, and the capacitor 246. A signalreceived at the input 104 is applied to a terminal 202 of the resistor204, a terminal 208 of the resistor 210, and a terminal 214 of theresistor 216; a signal received at the input 108 is applied to a switchcontrol terminal 230 of the switch 232, and a switch control terminal211 of the switch 213; a signal received at the input 110 is applied toa switch control terminal 222 of the switch 224 and switch controlterminal 396 of switch 398; a signal received at the input 112 isapplied to a switch control terminal 284 of the switch 286; a signalreceived at the input 114 is applied to a switch control terminal 304 ofthe switch 306, and a switch control terminal 270 of the switch 272; anda signal received at the input 116 is applied to a switch controlterminal 318 of the switch 320. Switches 222, 232, 213, 398, 320 and 306may each be implemented as a CMOS transmission gate, in which an NMOStransistor and a PMOS transistor are connected in parallel with eachother, the gate of the PMOS transistor is connected to the output of aninverter, the input of the inverter and the gate of the NMOS transistorare connected to each other and serve as the switch control terminal,and the source and drain of each transistor serve as the switchterminals. When a CMOS transmission gate is closed, the NMOS transistorand the PMOS transistor are active, such that a signal received on oneterminal of the CMOS transmission gate is conveyed to the other terminalof the CMOS transmission gate. When a CMOS transmission gate is open,the NMOS transistor and the PMOS transistor are not active, such that asignal received on one terminal of the CMOS transmission gate is notconveyed to the other terminal of the CMOS transmission gate.

[0033] The variable gain input stage associated with the firstintegrator may amplify the signal received at the input 104 by one ofthree amplification factors and produce an output signal at a node 217.If the signals received at the inputs 108 and 110 are a logical zerovoltage level (i.e., ground potential) and a logical zero voltage level,respectively, the variable gain input stage amplifies the signalreceived at the input 104 by a relatively low amplification factor. Inthe present embodiment, the relatively low amplification factor may beone-tenth. If the signals received at the inputs 108 and 110 are alogical zero voltage level and a logical one voltage level (i.e., 5V),respectively, the variable gain input stage amplifies the signalreceived at the input 104 by a relatively moderate amplification factor.In the present embodiment, the relatively moderate amplification factoris one. If the signals received at the inputs 108 and 110 are a logicalone voltage level and a logical zero voltage level, respectively, thevariable gain input stage amplifies the signal received at the input 104by a relatively high amplification factor. In the present embodiment,the relatively high amplification factor is ten. In the presentembodiment, the signals received at the inputs 108 and 110 should neverboth be a logical one voltage level.

[0034] The other terminal 206 of the resistor 204 is coupled to aterminal 226 of the switch 224, a terminal 234 of the switch 232, aninverted input 236 of the operational amplifier 240, a terminal 244 ofthe capacitor 246, a terminal 250 of the resistor 252, a terminal 290 ofthe resistor 292, a terminal 296 of the resistor 298 and a terminal 310of the resistor 312, all of which form a node 217. In the presentembodiment, the resistor 204 has a resistance of 200 kΩ.

[0035] The other terminal 212 of the resistor 210 is connected to aterminal 220 of the switch 224. In the present embodiment, the resistor210 has a resistance of 22.22 kΩ. The terminal 226 of the switch 224 isconnected to the node 217. The switch 224 closes to connect its terminal220 to its other terminal 226 if the signal received at the switchcontrol terminal 222 is a logical one voltage level. If the signal atthe switch control terminal 222 is at a logical zero voltage level, theswitch 224 opens to disconnect its other terminal 220 from its terminal226 resulting in an open circuit between those terminals.

[0036] The other terminal 218 of the resistor 216 is connected to aterminal 228 of the switch 232. In the present embodiment, the resistor216 has a resistance of 2.02 kΩ. The terminal 234 of the switch 232 isconnected to the node 217. The switch 232 closes to connect its terminal228 to its other terminal 234 if the signal received at its switchcontrol terminal 230 is a logical one voltage level. If the signal atthe switch control terminal 230 is a logical zero voltage level, theswitch 232 opens to disconnect its terminal 228 from its other terminal234 resulting in an open circuit between those terminals.

[0037] The first integrator filters the signal received at the node 217and produces a signal at a node 219, which is formed by the commonconnection of the other terminal 254 of the resistor 252, an output 242of the operational amplifier 240, the other terminal 248 of thecapacitor 246, the terminal 256 of the resistor 258, the terminal 262 ofthe resistor 264, the terminal 276 of the resistor 278, the terminal 358of the resistor 360 and the output 118. The other terminal 254 of theresistor 252 is connected to the node 219. In the present embodiment,the resistor 254 has a resistance of 20 kΩ. The other terminal 248 ofthe capacitor 246 is connected to the node 219. In the presentembodiment, the capacitor 246 has a capacitance of 80 pF. In the presentembodiment, the operational amplifier 240 is a model LF347 operationalamplifier available from National Semiconductor Corporation of SantaClara, Calif.

[0038] The variable gain output stage associated with the firstintegrator may amplify the signal received at the node 219 by one ofthree factors and produce an amplified signal at the output 122. If thesignals received at the inputs 108 and 110 are a logical zero voltagelevel and a logical zero voltage level, respectively, the variable gainoutput stage amplifies the signal received at the node 219 by arelatively high amplification factor. In the present embodiment, therelatively high amplification factor may be ten. If the signals receivedat the inputs 108 and 110 are a logical zero voltage level and a logicalone voltage level, respectively, the variable gain output stageamplifies the signal received at the node 219 by a relatively moderateamplification factor. In the present embodiment, the relatively moderateamplification factor is one. If the signals received at the inputs 108and 110 are a logical one and a logical zero voltage level,respectively, the variable output gain stage amplifies the signalreceived at the node 219 by a relatively low amplification factor. Inthe present embodiment, the relatively low amplification factor isone-tenth. In the present embodiment, the signals received at the inputs108 and 110 should never both be a logical one voltage level.

[0039] The other terminal 370 of the resistor 360 is connected to aninverted input 374 of the operational amplifier 376, a terminal 382 ofthe resistor 384, a terminal 388 of the resistor 390, and a terminal 203of the resistor 205. The common connection of the other terminal 370 ofthe resistor 360, the inverted input 374 of the operational amplifier376, the terminal 382 of the resistor 384, the terminal 388 of theresistor 390, and the terminal 203 of the resistor 205 form a node 225.In the present embodiment, the resistor 360 has a resistance of 20 kΩ.In the present embodiment, the operational amplifier 376 is a modelLF347 operational amplifier available from National SemiconductorCorporation of Santa Clara, Calif. The other terminal 386 of theresistor 384 is connected to the output 122 of the main filter 106. Inthe present embodiment, the resistor 384 has a resistance of 200 kΩ.

[0040] The other terminal 392 of the resistor 390 is connected to aterminal 394 of the switch 398. In the present embodiment, the resistor390 has a resistance of 22.22 kΩ. The other terminal 201 of the switch398 is connected to the output 122 of the main filter 106. The switch398 closes to connect its terminal 394 to its other terminal 201 if thesignal received at the switch control terminal 396 is a logical onevoltage level. If the signal at the switch control terminal 396 is alogical zero voltage level, the switch 398 opens to disconnect itsterminal 394 from its other terminal 201 resulting in an open circuitbetween those terminals.

[0041] The other terminal 207 of the resistor 205 is connected to aterminal 209 of the switch 213. In the present embodiment, the resistor205 has a resistance of 2.02 kΩ. The other terminal 215 of the switch213 is connected to the output 122 of the main filter 106. The switch213 closes to connect its terminal 209 to its other terminal 215 if thesignal received at the switch control terminal 211 is a logical onevoltage level. If the signal at the switch control terminal 211 is alogical zero voltage level, the switch 213 opens to disconnect itsterminal 209 from its other terminal 215 resulting in an open circuitbetween those terminals.

[0042] The variable gain input stage associated with the secondintegrator may amplify the signal received at the node 219 by one ofthree factors and produce an output signal at a node 221, at which theother terminal 288 of the switch 286, the other terminal 274 of theswitch 272, the other terminal 260 of resistor 258, one terminal 332 ofthe capacitor 334 and the inverting impact of the operational amplifier328 are commonly connected. If the signals received at the inputs 112and 114 are a logical zero voltage level and a logical zero voltagelevel, respectively, the variable gain input stage amplifies the signalreceived at the node 221 by a relatively low amplification factor. Inthe present embodiment, the relatively low factor is one-tenth. If thesignals received at the inputs 112 and 114 are a logical zero voltagelevel and a logical one voltage level, respectively, the variable gaininput stage amplifies the signal received at the node 221 by arelatively moderate amplification factor. In the present embodiment, therelatively moderate amplification factor is one. If the signals receivedat the inputs 112 and 114 are a logical one voltage level and a logicalzero voltage level, respectively, the variable gain input stageamplifies the signal received at the node 221 by a relatively highamplification factor. In the present embodiment, the relatively highamplification factor is ten. In the present embodiment, the signalsreceived at the inputs 112 and 114 should never both be a logical onevoltage level. The other terminal 260 of the resistor 258 is connectedto node 221. In the present embodiment, the resistor 258 has aresistance of 10 kΩ.

[0043] The other terminal 266 of the resistor 264 is connected to oneterminal 268 of the switch 272. In the present embodiment, the resistor264 has a resistance of 1.11 kΩ. The other terminal 274 of the switch272 is connected to the node 221. The switch 272 closes to connect itsterminal 268 to its other terminal 274 if the signal received at theswitch control terminal 270 is a logical one voltage level. If thesignal at the switch control terminal 270 is a logical zero voltagelevel, the switch 272 opens to disconnect its terminal 268 from itsother terminal 274 resulting in an open circuit between those terminals.

[0044] The other terminal 280 of the resistor 278 is connected to oneterminal 282 of the switch 286. In the present embodiment, the resistor278 has a resistance of 0.10 kΩ. The other terminal 288 of the switch286 is connected to the node 221. The switch 286 closes to connect itsterminal 282 to its other terminal 288 if the signal received at theswitch control terminal 284 is a logical one voltage level. If thesignal at the switch control terminal 284 is a logical zero voltagelevel, the switch 286 opens to disconnect its terminal 282 from itsother terminal 288 resulting in an open circuit between those terminals.

[0045] The second integrator filters the signal received at the node 221and produces a filtered signal at the output 120 of the main filter 106.The other terminal 336 of the capacitor 334 is connected to the output120. In the present embodiment, the capacitor 334 has a capacitance of80 pF.

[0046] The output 330 of the operational amplifier 328 is connected tothe output 120 of the main filter 106. In the present embodiment, theoperational amplifier 328 may be implemented using a model LF347operational amplifier available from National Semiconductor Corporationof Santa Clara, Calif.

[0047] The variable gain output stage associated with the secondintegrator may amplify the signal received at terminal 338 of theresistor 340 by one of three factors and produce an amplified signal atthe node 217. If the signals received at the inputs 116 and 114 are alogical zero voltage level and a logical zero voltage level,respectively, the variable gain output stage amplifies the signalreceived at terminal 338 of the resistor 340 by a relatively lowamplification factor. In the present embodiment, the relatively lowamplification factor is one-tenth. If the signals received at the inputs116 and 114 are a logical zero voltage level and a logical one voltagelevel, respectively, the variable gain output stage amplifies the signalreceived at terminal 338 of the resistor 340 by a relatively moderateamplification factor. In the present embodiment, the relatively moderateamplification factor is one. If the signals received at the inputs 116and 114 are a logical one voltage level and a logical zero voltagelevel, respectively, the variable gain output stage amplifies the signalreceived at terminal 338 of the resistor 340 by a relatively highamplification factor. In the present embodiment, the relatively highamplification factor is ten. In the present embodiment, the signalsreceived at the inputs 116 and 114 should never both be a logical onevoltage level.

[0048] The terminal 338 of the resistor 340 is coupled to the output120. The other terminal 342 of the resistor 340 corresponds with aninverted input 344 of the operational amplifier 348 and the otherterminal 352 of the resistor 354. In the present embodiment, theresistor 340 has a resistance of 10 kΩ.

[0049] The terminal 356 of the resistor 354 is connected to the node223, at which the terminal 356 of resistor 354, the output 350 of theoperational amplifier 348, the other terminal 394 of the resistor 292,the other terminal 308 of the switch 306 and the other terminal 322 ofthe switch 320 are commonly connected. In the present embodiment, theresistor 354 has a resistance of 10 kΩ.

[0050] The output 350 of the operational amplifier 348 is connected tothe node 223. In the present embodiment, the operational amplifier 348is implemented using the model LF347 operational amplifier availablefrom National Semiconductor Corporation of Santa Clara, Calif. In thepresent embodiment, the resistor 292 has a resistance of 10 kΩ.

[0051] The other terminal 300 of the resistor 298 is connected toterminal 302 of the switch 306. In the present embodiment, the resistor298 has a resistance of 1.11 kΩ. The other terminal 308 of the switch306 is connected to the node 223. The switch 306 closes to connect itsterminal 302 to its other terminal 308 if the signal received at theswitch control terminal 304 is a logical one voltage level. If thesignal at the switch control terminal 304 is a logical zero voltagelevel, the switch 306 opens to disconnect its terminal 302 from itsother terminal 308 resulting in an open circuit between those terminals.

[0052] The other terminal 314 of the resistor 312 is connected to aterminal 316 of the switch 320. In the present embodiment, the resistor312 has a resistance of 0.10 kΩ. The other terminal 322 of the switch320 is connected to the node 223. The switch 320 closes to connect itsterminal 316 to its other terminal 322 if the signal received at theswitch control terminal 318 is a logical one voltage level. If thesignal at the switch control terminal 318 is a logical zero voltagelevel, the switch 320 opens to disconnect its terminal 316 from itsother terminal 322 resulting in an open circuit between those terminals.

[0053]FIG. 4 illustrates an exemplary embodiment of the switching unit130 as shown in FIG. 2. The switching unit 130 includes an input 124, aninput 126, an input 128, a first switch 406, a second switch 416 and anoutput 132. The switching unit 130 provides one of the signals receivedat the inputs 124, 126 to the output 132 in response to a signalreceived at the input 128.

[0054] A signal received at the input 124 is applied to one terminal 402of the first switch 406; a signal received at the input 126 is appliedto one terminal 412 of the second switch 416; and a signal received atthe input 128 is applied to a switch control terminal 404 of the firstswitch 406 and an inverting switch control terminal 414 of the secondswitch 416. The first switch 406 closes to connect its terminal 402 toits other terminal 408 if the signal received at the switch controlterminal 404 is a logical one voltage level (i.e., 5 V). If the signalat the switch control terminal 404 is a logical zero voltage level(i.e., ground potential), the first switch 406 opens to disconnect itsterminal 402 from its other terminal 408 resulting in an open circuitbetween those terminals. The other terminal 408 of the first switch 406is connected to the output 132 of the switching unit 130.

[0055] The second switch 416 closes to connect its terminal 412 to itsother terminal 418 if the signal received at the inverting switchcontrol terminal 414 is a logical one voltage level. If the signal atthe inverting switch control terminal 414 is a logical zero voltagelevel, the second switch 416 opens to disconnect its terminal 412 fromits other terminal 418 resulting in an open circuit between thoseterminals. The other terminal 418 of the first switch 416 is connectedto the output 132 of the switching unit 130.

[0056]FIG. 10 illustrates the comparator 136. The comparator 136includes an input 134, an output 138, a comparator circuit 1006, and areference voltage 1003. The comparator circuit 1006 has an input 1002,an input 1004, and an output 1008. In the present embodiment, thecomparator 136 may be implemented using a model LM219 comparatoravailable from National Semiconductor Corporation of Santa Clara, Calif.The input 1002 is connected to the input 134, the input 1004 isconnected to the reference voltage 1003, and the output 1008 isconnected to the output 138. In the present embodiment, the referencevoltage 1003 is ground. The comparator circuit 1006 measures a signalreceived at the input 1002 against the reference voltage 1003 receivedat the input 1004. If the voltage of the signal received at the input1002 is approximately equal to the reference voltage 1003 received atthe input 1004, the comparator circuit 1006 produces a logical onevoltage level signal at the output 1008. If the voltage of the signalreceived at the input 1002 is not approximately equal to the referencevoltage 1003, the comparator circuit 1006 produces a logical zerovoltage level signal at the output 1008. The output 138 of thecomparator 136 is connected to the clock input 140 of the shift register144.

[0057]FIG. 5 illustrates an exemplary embodiment of the shift register144 as shown in FIG. 2. The shift register 144 includes an clock input140, an input 142, a first positive edge triggered D-type flip flop 508,a second positive edge triggered D-type flip flop 518, a third positiveedge triggered D-type flip flop 528, a two input OR gate 532, an output146, an output 148 and an output 150. The shift register 144 indicateswhich of the first and second integrators have reached the referencevoltage. A signal received at the clock input 140 is applied to a clockinput 506 of the first positive edge triggered D-type flip flop 508, aclock input 516 of the second positive edge triggered D-type flip flop518, and a clock input 526 of the third positive edge triggered D-typeflip flop 528; and a signal received at the input 142 is applied to apreset/enable input 504 of the first positive edge triggered D-type flipflop 508, a reset/enable input 514 of the second positive edge triggeredD-type flip flop 518, and a reset/enable input 524 of the third positiveedge triggered D-type flip flop 528.

[0058] The first positive edge triggered D-type flip flop 508 produces alogical zero voltage level signal (i.e., ground potential) on its dataoutput 510 if a signal received at the preset/enable input 504 is equalto a logical one voltage level (i.e., 5 V). If the signal received atthe preset/enable input 504 is equal to a logical zero voltage level,the first positive edge triggered D-type flip flop 508 causes a signalreceived at its data input 502, which is connected to ground, to beprovided at its data output 510 each time a positive transition of asignal from a logical zero voltage level to a logical one voltage levelis received by its clock input 506. The output 510 is connected to thedata input 512 of the second positive edge triggered D-type flip flop518, and the output 146.

[0059] The second positive edge triggered D-type flip flop 518 producesa logical zero voltage level signal on its data output 520 if a signalreceived at the reset/enable input 514 is equal to a logical one voltagelevel. If the signal received at the reset/enable input 514 is equal toa logical zero voltage level, the second positive edge triggered D-typeflip flop 518 causes a signal received at its data input 512 to beprovided at its data output 520 at each time a positive transition of asignal from a logical zero voltage level to a logical one voltage levelis received by its clock input 516. The data input 512 of the secondpositive edge triggered D-type flip-flop 518 is connected to the dataoutput 510 of the first positive edge triggered D-type flip flop 508 andthe output 146 of the shift register 144. The data output 520 isconnected to one input of the two input OR gate 532 and the output 148of the shift register 144.

[0060] The third positive edge triggered D-type flip flop 528 produces alogical zero voltage level signal on its data output 530 if a signalreceived at its reset/enable input 524 is equal to a logical one voltagelevel. If the signal received at the reset/enable input 524 is equal toa logical zero voltage level, the third positive edge triggered D-typeflip flop 528 causes a signal received at its data input 522 to beprovided at its data output 530 each time a positive transition of asignal from a logical zero voltage level to a logical one voltage levelis received by its clock input 526. The data input 522 of the thirdpositive edge triggered D-type flip-flop 528 is connected to the outputof the two input OR gate 532. The data output 530 of the third positiveedge triggered D-type flip-flop 528 is connected to the other input ofthe two input OR gate 532 and the output 150 of the shift register 144provide more explanation of how the shift register determines which ofthe outputs of the integrators of the main filter 106 the comparatorshould measure against the reference voltage.

[0061] Referring to FIG. 6, there is shown an exemplary embodiment ofthe strength detector 154 as shown in FIG. 2. The strength detector 160includes an input 152, a peak detector 604, a first threshold detector610, a second threshold detector 616, a first inverter gate 622, asecond inverter gate 628, a third inverter gate 634, a first output 156,and a second output 158. The peak detector 604 and the first thresholddetector 610 are described in more detail below with reference to FIG. 7and FIG. 8, respectively. The strength detector 154 senses the voltageenvelope of the signal received at the input 152, and decides whether itwould be appropriate to change amplification factors of the variablegain stages of the main filter 106. The saturation threshold representsthe strength of the input signal received by the main filter 106 atwhich the main filter 106 approaches saturation given the presentamplification factors of the main filter 106. The noise floor thresholdrepresents the strength of the input signal received by the main filter106 at which the output signal of the main filter 106 has a minimumacceptable signal-to-noise ratio given the present amplification factorsof the main filter 106.

[0062] A signal received at the input 152 of the strength detector 154is applied to an input 602 of the peak detector 604. The peak detector604 receives an input voltage signal at its input 602 and provides acurrent signal representative of the peak of the voltage envelope of theinput signal at its output 606. The output 606 of the peak detector 604is coupled to an input 608 of the first threshold detector 610 and aninput 614 of the second threshold detector 616. The first thresholddetector 610 provides a logical one voltage level on its output 612 ifthe signal at its input 608 has a voltage envelope peak greater than thesaturation threshold, and provides a logical zero voltage level on itsoutput 612 if the signal at the input 608 has a voltage envelope peakless than the saturation threshold limit. The output 612 of the firstthreshold detector 610 is coupled to an input 620 of the first invertergate 622. The second threshold detector 616 provides a logical onevoltage level on its output 618 if the signal at its input 614 has avoltage envelope peak greater than the noise floor threshold, andprovides a logical zero voltage level on its output 618 if the signal atits input 614 has a voltage envelope peak less than the noise floorthreshold. The output 618 of the second threshold detector 616 iscoupled to the input 632 of the third inverter gate 634.

[0063] The inverter gate 622 inverts the signal received at its input620 and provides the inverted signal at its output 624. The output 624is connected to the input 626 of the second inverter gate 628. Thesecond inverter gate 628 inverts the signal received at its input 626and provides the inverted signal at the output 630. The output 630 iscouple to the first output 156 of the strength detector 154. The thirdinverter gate 634 inverts the signal received at its input 632 andprovides the inverted signal at its output 636. The output 636 isconnected to the second output 158 of the strength detector 154.

[0064]FIG. 7 illustrates an exemplary embodiment of the peak detector604 of the strength detector 154 of FIG. 6. The peak detector 604includes an NMOS transistor Q₁, a PMOS transistor Q₃, an NMOS transistorQ₄, a PMOS transistor Q₅, a PMOS transistor Q₆, a capacitor 750, aresistor 758, and a transconductor 742.

[0065] A signal received by the input 602 of the peak detector 604 isapplied to a positive input 744 of the transconductor 742. Thetransconductor 742 provides at its output 748 a signal which is equal tothe difference in the signal received by its positive input 744 and thesignal received by the negative input 746, which is connected to ground,scaled by a transconductance G_(in) of the transconductor 742. In thepresent embodiment the transconductor 742 has a transconductance G_(in)of 1 microampere per volt. The current signal provided at the output 748of the transconductor 742 is applied to the gate 710 of the PMOStransistor Q₃ and the gate 724 of the NMOS transistor Q₄, which areconnected to form an inverter, the gate 726 and the drain 732 of thediode connected PMOS transistor Q₅, the drain 736 and the backgate 738of the PMOS transistor Q₆, and the drain 702 of the NMOS transistor Q₁.The inverter formed by the PMOS transistor Q₃ and the NMOS transistor Q₄are connected between supply voltages V_(DD) and V_(SS), and thecommonly connected drains of PMOS transistor Q₃ and NMOS transistor Q₄are connected to the source 728 of the diode connected PMOS transistorQ₅ and the gate 734 of PMOS transistor Q₆. The back gates 714 and 720 ofthe PMOS transistor Q₃ and the NMOS transistor Q₄ are connected tosupply voltages V_(DD) and V_(SS), respectively. The commonly connectedgate 726 and drain 732 of the diode connected PMOS transistor Q₅ areconnected to the drain 736 and backgate 738 of PMOS transistor Q₆. Theback gate 730 of diode connected PMOS transistor is connected to supplyvoltage V_(DD). The source 740 of the PMOS transistor Q₆ is connected tothe gate 748 of NMOS transistor Q₁, one terminal of capacitor 750, oneterminal 756 of the resistor 758 and the output terminal 606 of the peakdetector 606. The other terminal 754 of the capacitor 750 and the otherterminal 1060 of the resistor 758 are connected to supply voltageV_(SS). The drain 702 of NMOS transistor Q₁ is connected to the output748 of the transconductor 742, the drain 736 and the backgate 738 ofPMOS transistor Q₆, the commonly connected gate 726 and drain 732 of thediode connected PMOS transistor Q₅, and the commonly connected gates 710and 724 of the PMOS transistor Q₃ and the NMOS transistor Q₄ forming theinverter. The source 706 of the NMOS transistor Q₁ is connected tosupply voltage V_(SS).

[0066] The NMOS transistor Q₁ of the peak detector 604 forms half of aNMOS current mirror. The other half of the current mirror consists of anNMOS transistor Q₂ of the threshold detector 610 (shown in FIG. 8).Thus, when the output 606 of the peak detector 604 is connected to theinput 608 of the threshold detector 610, a complete NMOS current mirroris formed which acts as a current memory storing the peak current, i.e.,the current that represents the voltage envelope peak of input signal ofthe main filter. The CMOS inverter formed by PMOS transistor Q₃ and NMOStransistor Q₄ acts as a current comparator which compares the currentprovided by the output 748 of the transconductor 742 with the draincurrent of NMOS transistor Q₁.

[0067] When the drain current of NMOS transistor Q₁ is larger that thecurrent provided by the output 748 of the transconductor 742, thecommonly connected gates 710 and 724 of the PMOS transistor Q₃ and theNMOS transistor Q₄ forming the inverter are at a logical zero voltagelevel (i.e., V_(SS)) and the commonly connected drains 716 and 718 ofthose transistors are at a logical one voltage level (i.e., V_(DD)).Because the gate 734 of PMOS transistor Q₆ is connected to the commonlyconnected drains 716 and 718 of the inverter transistors Q₃ and Q₄, itis also at the logical one voltage level, and the PMOS transistor Q₆ isturned off. If the current provided by the output 748 of thetransconductor 742 becomes larger than the drain current of NMOStransistor Q₁, the commonly connected gates 710 and 724 of PMOStransistor Q₃ and NMOS transistor Q₄ switches to a logical one voltagelevel, and the commonly connected drains 716 and 718 of thosetransistors switches to a logical zero voltage level; this causes thegate 734 of the PMOS transistor Q₆ to go to the logical zero voltagelevel and the PMOS transistor Q₆ to turn on. In this manner, PMOStransistor Q₆ connects the gates 708 and 802 (shown in FIG. 8) of NMOStransistors Q₁ and Q₂, terminal 752 of capacitor 750 and terminal 756 ofthe resistor 758 to the output 748 of the transconductor 742, and thecurrent mirror follows the current provided by the output 748 oftransconductor 742. When the current provided by the output 748 of thetransconductor 742 starts to fall below the new peak current, thecommonly connected gates 710 and 724 of PMOS transistor Q₃ and NMOStransistor Q₄ switch back to the logical zero voltage level and thecommonly connected drains of those transistors to switch back to alogical one voltage level. This causes the PMOS transistor Q₆ to turnoff leaving the gates 708 and 802 (shown in FIG. 8) of NMOS transistorsat the voltage on the terminal 752 of the capacitor 750, thus allowingthe NMOS current mirror to hold the new peak current, though the newpeak current degrades as the capacitor 750 discharges through theresistor 758. Thereafter, the diode connected PMOS transistor Q₅ startsto supply the difference between the current provided by the output 748of the transconductor 742 and the drain current of the NMOS transistorQ₁ to the node formed by the output 748 of the transconductor 743, thedrain of NMOS transistor Q₁ and the commonly connected gates 710 and 724of the PMOS transistor Q₃ and the NMOS transistor Q₄.

[0068]FIG. 8 illustrates an exemplary embodiment of the first thresholddetector 610 of the strength detector 160 of FIG. 6. The first thresholddetector 610 compares the current representing of the voltage envelopepeak of a signal received at the input 602 of the peak detector 604 to areference current supplied by a current source 826. The first thresholddetector 610 includes an NMOS transistor Q₂, a PMOS transistor Q₇, aPMOS transistor Q₈, the current source 826 and an output 612 of thefirst threshold detector 610. Any number of threshold detectors can beconnected to the peak detector 604 to derive a corresponding number ofsignal strength detector outputs.

[0069] As explained above in connection with FIG. 7, the NMOS transistorQ₂ of the first threshold detector 610 forms half of an NMOS currentmirror that acts as a current memory which stores the peak currentcorresponding to the voltage envelope peak of the signal received at theinput 602 of the peak detector 604. The other half of the NMOS currentmirror that acts as a current memory consists of the NMOS transistor Q₁of the peak detector 604, shown in FIG. 7, which has its gate 708connected (via the output 606 of the peak detector 604) to the input 608of the first threshold detector 610. The input 608 is connected to thegate 802 of NMOS transistor Q₂ to form a complete NMOS current mirror.The source 808 and the backgate 806 of the NMOS transistor Q₂ areconnected to supply voltage V_(SS). The drain 804 of the NMOS transistorQ₂ is connected to the drain 810 of the PMOS transistor Q₇.

[0070] The NMOS transistor Q₇, the NMOS transistor Q₈ and the currentsource 826 form a current mirror that causes a current to flow throughthe NMOS transistor Q₇ that mirrors the current of the current source826. The gate 814 of the NMOS transistor Q₇ is connected to the gate 818of the NMOS transistor Q₈, the drain 820 of the NMOS transistor Q₈, andthe positive terminal 822 of the current source 826. The source 812 ofthe NMOS transistor Q₇ and the source 816 of NMOS transistor areconnected to supply voltage V_(DD). The drain 810 of the NMOS transistorQ₇ is connected to the drain 804 of the NMOS transistor Q₂ and theoutput 612 of the threshold detector 610. The negative terminal 824 ofthe current source 826 is connected to ground.

[0071] The current source 826 produces a reference current thatrepresents the threshold voltage of the first threshold detector 610.The reference current can be any value, for example 100 uA, and thetransistors Q₇, Q₈ of the first threshold detector 610 are scaled tocause the desired current to flow through the transistor Q₇. Thepreferred form of a current source is a resistance connected between thedrain 820 of NMOS transistor Q₈ and ground. In the present example thereference current generated by the current source in the first thresholddetector 610 is 5.5 mA.

[0072] The output 612 of the first threshold detector 610 indicateswhether the respective amplification factors of the main filter 106should be decreased given the voltage envelope of the signal received atthe input 602 of the peak detector 604. If the current flowing throughthe transistor Q₂, which represents the voltage envelope peak of thesignal received at the input 602 of the peak detector 604 (shown in FIG.7), exceeds the current flowing through the transistor Q₇, which isrelated to the reference current of the current source 826, the output612 of the first threshold detector 610 will be at a logical zerovoltage level. If the current flowing through the transistor Q₂ does notexceed the current flowing through the transistor Q₇, the output 612 ofthe first threshold detector 610 will be at a logical one voltage level.In this manner, the saturation threshold limit of the signal strengthdetector 154 is represented by the amount of current generated by thecurrent source 826.

[0073] In an exemplary embodiment the second threshold detector 616 (notshown in FIG. 8) is similar to the first threshold detector 610 shown inFIG. 8. It has a counterpart to NMOS transistor Q₂ of the firstthreshold detector 610, with the gate of the counterpart transistorconnected to the output 606 of the peak detector 604. The secondthreshold detector 616 also has its counterpart to the current mirror,which in the first threshold detector 610 consists of NMOS transistorsQ₇ and Q₈, and reference current source 826. The counterpart to thecurrent source 826 of the second threshold detector 616 would produce areference current that represents the noise floor threshold limit. Inthe present example, the counterpart to the current source 826 generates55 micro-amperes.

[0074] FIGS. 9(a) and 9(b) illustrate an exemplary embodiment of thegain control unit 172. The gain control unit 172 provides signals thatcontrol the various variable gain stages of the main filter 106, theswitching unit 130, and the shift register 144. The gain control unit172 includes AND gates, OR gates, a positive edge triggered D-type flipflop 972, a positive edge triggered D-type flip flop 980, a positiveedge triggered D-type flip flop 988, a positive edge triggered D-typeflip flop 996, and an N-bit binary counter 911. The gain control unit172 receives control signals at its inputs 160, 162, 166, 168, 170,which are applied to an array of AND gates, and a clock signal at theinput 985, which is applied to clock inputs 970, 978, 986, and 994 ofthe positive edge triggered D-type flip flops 972, 980, 988, and 996,respectively, and clock input 909 of the N-bit counter 911.

[0075] When the signal received at the system input 102 changes from arelatively small signal, needing a relatively large amount ofamplification to be processed effectively (i.e., without saturation ofthe main filter 106 or having the main filter 106 provide an outputsignal having greater than the minimum acceptable signal to noiseratio), to a relatively medium strength signal, needing a relativelymoderate amount of amplification to be processed effectively, the gaincontrol unit 172 changes the respective amplification factors of thevariable gain stages of the main filter 106 accordingly. If the signalprocessing system 100 is adapted to process a relatively small inputsignal, logical one voltage level signals are be produced on the outputs178 and 184 of the gain control unit 172, and logical zero voltage levelsignals are produced on outputs 176, 180, 182, and 186 of the gaincontrol unit 172. This corresponds to the application of logical onevoltage level signals on inputs 108 and 114 of the main filter 106 ofFIG. 3, and the application of logical zero voltage level signals oninputs 110, 112 and 116 of the main filter 106 of FIG. 3. In addition, alogical zero voltage level signal is applied to input 142 of the shiftregister 144 of FIG. 5. If these conditions exist, and the signalreceived at the input 162 of the gain control unit 172 is a logical onevoltage level signal, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter106. The logical one voltage level signal at the input 162 of the gaincontrol unit 172 is provided by output 158 of the strength detector 154to indicate that the main filter 160 is approaching saturation. The gaincontrol unit 172 begins the process of changing the respectiveamplification factors of variable gain stages of the main filter 106 byproviding a logical one voltage level signal on the output 176, withoutchanging any other output signals. Providing a logical one voltage levelsignal on the output 176 of the gain control unit 172 corresponds toapplying a logical one voltage level signal to reset/enable input 142 ofthe shift register 144, which enables the shift register 144. Once thegain control unit 172 receives a logical one voltage level signal at theinput 168, it produces logical one voltage level signals on the outputs176, 180, 182, and produces logical zero voltage level signals on theoutputs 178, 184, 186. The gain control unit 172 receives a logical onevoltage level signal at its input 168 when the comparator 136 determinesthat the output of the first integrator of the main filter 106 (output118), as provided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “100” state to the “010” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the first integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the first integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 168, the gaincontrol unit 172 provides logical one voltage level signals on itsoutputs 176, 180 and 182 to keep the shift register enabled, and tocause switches 224, 398 and 286 (shown in FIG. 3) to close, and provideslogical zero voltage level signals on its outputs 178, 184 and 186 tocause switches 232, 213, 272, 320 and 306 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator is changed from a relatively large value to arelatively moderate value, and the amplification factor of the variablegain output stage associated with the first integrator is changed to bethe reciprocal of that of the variable gain input stage associated withthe first integrator. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively moderate value to a relatively large value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. And then once the gain control unit 172 receives a logicalone voltage level signal at the input 170, the gain control unit 172produces logical one voltage level signals on the outputs 180, 184, andproduces logical zero voltage level signals on the outputs 176, 178,182, 186. The gain control unit 172 receives a logical one voltage levelsignal at its input 170 when the comparator 136 determines that theoutput of the second integrator of the main filter 106 (output 120), asprovided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “010” state to the “001” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the second integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the second integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 170, the gaincontrol unit 172 provides logical one voltage level signals on itsoutputs 180 and 184 to cause switches 224, 398, 272 and 306 (shown inFIG. 3) to close, and provides logical zero voltage level signals on itsoutputs 176, 178, 182 and 186 to cause the shift register 144 to resetand switches 232, 213, 286 and 320 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator remains the same, and the amplification factor ofthe variable gain output stage associated with the first integratorremains the same. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively large value to a relatively moderate value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. Once this is completed, the gain control unit 172 hascompleted a desired change of the respective amplification factors ofthe variable gain stages of the main filter 106.

[0076] When the signal received at the system input 102 changes from arelatively medium strength signal, needing a relatively moderate amountof amplification to be processed effectively, to a relatively largesignal, needing a relatively small amount of amplification to beprocessed effectively, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter 106accordingly. If the signal processing system 100 is adapted to process arelatively medium strength input signal, logical one voltage levelsignals are produced on the outputs 180 and 184 of the gain control unit172, and logical zero voltage level signals are produced on outputs 176,178, 182, and 186 of the gain control unit 172. This corresponds to theapplication of logical one voltage level signals on inputs 110 and 114of the main filter 106 of FIG. 3, and the application of logical zerovoltage level signals on inputs 108, 112 and 116 of the main filter 106of FIG. 3. In addition, a logical zero voltage level signal is appliedto input 142 of the shift register 144 of FIG. 5. If these conditionsexist, and the signal received at the input 162 of the gain control unit172 is a logical one voltage level signal, and the signal received atthe input 160 of the gain control unit 172 is a logical zero voltagelevel signal, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter106. The logical one voltage level signal at the input 162 of the gaincontrol unit 172 is provided by output 158 of the strength detector 154to indicate that the main filter 160 is approaching saturation. The gaincontrol unit 172 begins the process of changing the respectiveamplification factors of the variable gain stages of the main filter 106by providing a logical one voltage level signal on the output 176, whileall other outputs remain unchanged. Providing a logical one voltagelevel signal on the output 176 of the gain control unit 172 correspondsto applying a logical one voltage level signal to reset/enable input 142of the shift register 144, which enables the shift register 144. Oncethe gain control unit 172 receives a logical one voltage level signal atthe input 168, the gain control unit 172 produces logical one voltagelevel signals on the outputs 176, 182, and produces logical zero voltagelevel signals on the outputs 178, 180, 184, 186. The gain control unit172 receives a logical one voltage level signal at its input 168 whenthe comparator 136 determines that the output of the first integrator ofthe main filter 106 (output 118), as provided to the comparator 136 bythe switching unit 130, is approximately equal to zero volts, and thecomparator 136 provides a logical zero to logical one voltage leveltransition at its output 138 to the clock input 140 of the shiftregister 144 causing the shift register 144 to change from the “100”state to the “010” state. Changing the respective amplification factorsof the variable gain stages of the main filter 106 while the output ofthe first integrator is approximately equal to zero volts avoids orminimizes the occurrence of transients in the signal produced at theoutput of the first integrator caused by the change in the amplificationfactors. Accordingly, once it receives a logical one voltage levelsignal at its input 168, the gain control unit 172 provides logical onevoltage level signals on its outputs 176 and 182 to keep the shiftregister enabled, and to cause the switch 286 (shown in FIG. 3) toclose, and provides logical zero voltage level signals on its outputs178, 180, 184 and 186 to cause switches 232, 213, 224, 398, 272, 306 and320 to open. In this manner, the amplification factor of the variablegain input stage associated with the first integrator is changed from arelatively moderate value to a relatively small value, and theamplification factor of the variable gain output stage associated withthe first integrator is changed to be the reciprocal of that of thevariable gain input stage associated with the first integrator. At thesame time, the amplification factor of the variable gain input stageassociated with the second integrator is changed from a relativelymoderate value to a relatively large value, and the amplification factorof the variable gain output stage associated with the second integratoris changed to be the reciprocal of that of the variable gain input stageassociated with the second integrator. And then once the gain controlunit 172 receives a logical one voltage level signal at the input 170,it produces a logical one voltage level signal on the output 184, andproduces logical zero voltage level signals on the outputs 176, 178,180, 182, 186. The gain control unit 172 receives a logical one voltagelevel signal at its input 170 when the comparator 136 determines thatthe output of the second integrator of the main filter 106 (output 120),as provided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “010” state to the “001” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the second integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the second integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 170, the gaincontrol unit 172 provides a logical one voltage level signal on itsoutput 184 to cause switches 272 and 306 (shown in FIG. 3) to close, andprovides logical zero voltage level signals on its outputs 176, 178,180, 182 and 186 to cause the shift register 144 to reset and switches232, 213, 224, 398, 286 and 320 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator remains the same, and the amplification factor ofthe variable gain output stage associated with the first integratorremains the same. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively large value to a relatively moderate value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. Once this is completed, the gain control unit 172 hascompleted the desired change of the respective amplification factors ofthe variable gain stages of the main filter 106.

[0077] When the signal received at the system input 102 changes from arelatively large signal, needing a relatively small amount ofamplification to be processed effectively, to a relatively mediumstrength signal, needing a relatively moderate amount of amplificationto be processed effectively, the gain control unit 172 changes therespective amplification factors of the variable gain stages of the mainfilter 106 accordingly. If the signal processing system 100 is adaptedto process a relatively large input signal, a logical one voltage levelsignal is produced on the output 184 of the gain control unit 172, andlogical zero voltage level signals will be produced on outputs 176, 178,180, 182, and 186 of the gain control unit 172. This corresponds to theapplication of logical one voltage level signals on inputs 114 of themain filter 106 of FIG. 3, and the application of logical zero voltagelevel signals on inputs 108, 110, 112 and 116 of the main filter 106 ofFIG. 3. In addition, a logical zero voltage level signal is applied toinput 142 of the shift register 144 of FIG. 5. If these conditionsexist, and the signal received at the input 162 of the gain control unit172 is a logical zero voltage level signal, and the signal received atthe input 160 of the gain control unit 172 is a logical one voltagelevel signal, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter106. The logical one voltage level signal at the input 160 of the gaincontrol unit 172 is provided by output 156 of the strength detector 154to indicate that the signal produced by the main filter 160 isapproaching the noise floor of the main filter 160. The gain controlunit 172 begins the process of changing the respective amplificationfactors of the variable gain stages of the main filter 106 by waiting aspecified period of time equal to the time it would take, given a worstcase input signal, for the main filter 106 to recover from a rapidchange in the input signal before increasing the respectiveamplification factors of the variable gain stages of the main filter 106will not overload any of the internal nodes of the main filter 106. Oncethe specified period of time has elapsed, the gain control unit 172provides a logical one voltage level signal on the output 176, while allother outputs remain unchanged. Providing a logical one voltage levelsignal on the output 176 of the gain control unit 172 corresponds toapplying a logical one voltage level signal to reset/enable input 142 ofthe shift register 144, which enables the shift register 144. Once thegain control unit 172 receives a logical one voltage level signal at theinput 168, the gain control unit 172 produces logical one voltage levelsignals on the outputs 176, 180, 186, and produces logical zero voltagelevel signals on the outputs 178, 182, 184. The gain control unit 172receives a logical one voltage level signal at its input 168 when thecomparator 136 determines that the output of the first integrator of themain filter 106 (output 118), as provided to the comparator 136 by theswitching unit 130, is approximately equal to zero volts, and thecomparator 136 provides a logical zero to logical one voltage leveltransition at its output 138 to the clock input 140 of the shiftregister 144 causing the shift register 144 to change from the “100”state to the “010” state. Changing the respective amplification factorsof the variable gain stages of the main filter 106 while the output ofthe first integrator is approximately equal to zero volts avoids orminimizes the occurrence of transients in the signal produced at theoutput of the first integrator caused by the change in the amplificationfactors. Accordingly, once it receives a logical one voltage levelsignal at its input 168, the gain control unit 172 provides logical onevoltage level signals on its outputs 176, 180 and 186 to keep the shiftregister enabled, and to cause switches 224, 398 and 320 (shown in FIG.3) to close, and provides logical zero voltage level signals on itsoutputs 178, 182 and 184 to cause switches 232, 213, 286, 272 and 306 toopen. In this manner, the amplification factor of the variable gaininput stage associated with the first integrator is changed from arelatively small value to a relatively moderate value, and theamplification factor of the variable gain output stage associated withthe first integrator is changed to be the reciprocal of that of thevariable gain input stage associated with the first integrator. At thesame time, the amplification factor of the variable gain input stageassociated with the second integrator is changed from a relativelymoderate value to a relatively small value, and the amplification factorof the variable gain output stage associated with the second integratoris changed to be the reciprocal of that of the variable gain input stageassociated with the second integrator. And then once the gain controlunit 172 receives a logical one voltage level signal at the input 170,it produces logical one voltage level signals on the outputs 180, 184,and produces logical zero voltage level signals on the outputs 176, 178,182, 186. The gain control unit 172 receives a logical one voltage levelsignal at its input 170 when the comparator 136 determines that theoutput of the second integrator of the main filter 106 (output 120), asprovided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “010” state to the “001” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the second integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the second integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 170, the gaincontrol unit 172 provides logical one voltage level signals on itsoutputs 180 and 184 to cause switches 224, 398, 272 and 306 (shown inFIG. 3) to close, and provides logical zero voltage level signals on itsoutputs 176, 178, 182 and 186 to cause the shift register 144 to resetand switches 232, 213, 286 and 320 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator remains the same, and the amplification factor ofthe variable gain output stage associated with the first integratorremains the same. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively small value to a relatively moderate value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. Once this is completed, the gain control unit 172 hascompleted the desired change of the respective amplification factors ofthe variable gain stages of the main filter 106.

[0078] When the signal received at the system input 102 changes from arelatively medium strength signal, needing a relatively moderate amountof amplification to be processed effectively, to a relatively smallsignal, needing a relatively large amount of amplification to beprocessed effectively, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter 106accordingly. If the signal processing system 100 is adapted to process arelatively medium strength input signal, logical one voltage levelsignals are produced on the outputs 180, 184 of the gain control unit172, and logical zero voltage level signals are produced on outputs 176,178, 182, and 186 of the gain control unit 172. This corresponds to theapplication of logical one voltage level signals on inputs 110 and 114of the main filter 106 of FIG. 3, and the application of logical zerovoltage level signals on inputs 108, 112 and 116 of the main filter 106of FIG. 3. In addition, a logical zero voltage level signal is appliedto input 142 of the shift register 144 of FIG. 5. If these conditionsexist, and the signal received at the input 162 of the gain controlunit. 172 is a logical zero voltage level signal, and the signalreceived at the input 160 of the gain control unit 172 is a logical onevoltage level signal, the gain control unit 172 changes the respectiveamplification factors of the variable gain stages of the main filter106. The logical one voltage level signal at the input 160 of the gaincontrol unit 172 is provided by output 156 of the strength detector 154to indicate that the signal produced by the main filter 160 isapproaching the noise floor of the main filter 160. The gain controlunit 172 begins the process of changing the respective amplificationfactors of the variable gain stages of the main filter 106 by waiting aspecified period of time equal to the time it would take, given a worstcase rapidly changing input signal, for the main filter 106 to recoverfrom a rapid change in the input signal before increasing the respectiveamplification factors of the variable gain stages of the main filter 106will not overload any of the internal nodes of the main filter 106. Oncethe specified period of time has elapsed, the gain control unit 172provides a logical one voltage level signal on the output 176, while allother outputs remain unchanged. Providing a logical one voltage levelsignal on the output 176 of the gain control unit 172 corresponds toapplying a logical one voltage level signal to reset/enable input 142 ofthe shift register 144, which enables the shift register 144. Once thegain control unit 172 receives a logical one voltage level signal at theinput 168, it produces logical one voltage level signals on the outputs176, 178, 186, and produces logical zero voltage level signals on theoutputs 180, 182, 184. The gain control unit 172 receives a logical onevoltage level signal at its input 168 when the comparator 136 determinesthat the output of the first integrator of the main filter 106 (output118), as provided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “100” state to the “010” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the first integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the first integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 168, the gaincontrol unit 172 provides logical one voltage level signals on itsoutputs 176, 178 and 186 to keep the shift register enabled, and tocause switches 232, 213 and 320 (shown in FIG. 3) to close, and provideslogical zero voltage level signals on its outputs 180, 182 and 184 tocause switches 224, 398, 286, 272 and 306 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator is changed from a relatively moderate value to arelatively large value, and the amplification factor of the variablegain output stage associated with the first integrator is changed to bethe reciprocal of that of the variable gain input stage associated withthe first integrator. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively moderate value to a relatively small value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. And then once the gain control unit 172 receives a logicalone voltage level signal at the input 170, the gain control unit 172produces logical one voltage level signals on the output 178, 184, andproduces logical zero voltage level signals on the outputs 176, 180,182, 186. The gain control unit 172 receives a logical one voltage levelsignal at its input 170 when the comparator 136 determines that theoutput of the second integrator of the main filter 106 (output 120), asprovided to the comparator 136 by the switching unit 130, isapproximately equal to zero volts, and the comparator 136 provides alogical zero to logical one voltage level transition at its output 138to the clock input 140 of the shift register 144 causing the shiftregister 144 to change from the “010” state to the “001” state. Changingthe respective amplification factors of the variable gain stages of themain filter 106 while the output of the second integrator isapproximately equal to zero volts avoids or minimizes the occurrence oftransients in the signal produced at the output of the second integratorcaused by the change in the amplification factors. Accordingly, once itreceives a logical one voltage level signal at its input 170, the gaincontrol unit 172 provides logical one voltage level signals on itsoutputs 178 and 184 to cause switches 232, 213, 272 and 306 (shown inFIG. 3) to close, and provides logical zero voltage level signals on itsoutputs 176, 180, 182 and 186 to cause the shift register 144 to resetand switches 224, 398, 286 and 320 to open. In this manner, theamplification factor of the variable gain input stage associated withthe first integrator remains the same, and the amplification factor ofthe variable gain output stage associated with the first integratorremains the same. At the same time, the amplification factor of thevariable gain input stage associated with the second integrator ischanged from a relatively small value to a relatively moderate value,and the amplification factor of the variable gain output stageassociated with the second integrator is changed to be the reciprocal ofthat of the variable gain input stage associated with the secondintegrator. Once this is completed, the gain control unit 172 hascompleted the desired change of the respective amplification factors ofthe variable gain stages of the main filter 106.

[0079] The N-bit counter 911 receives a signal at an enable/reset input907, and a signal at a clock input 909, and provides an output at acounter overflow output 913. If the signal received at the input 907 isa logical one voltage level signal, the N-bit counter 911 increments onthe positive edge (i.e., a transition from a logical zero voltage levelto a logical one voltage level) of each clock cycle, and the signalproduced at the counter overflow output 913 is a logical zero, until theN-bit counter 911 reaches a specified maximum value. On the clock cycleafter the N-bit counter 911 reaches its specified maximum value, thesignal produced at the counter overflow output 913 is a logical onevoltage level signal. If the signal received at the input 907 is alogical zero voltage level signal, the N-bit counter 911 is reset to apredetermined state, and the signal produced at the counter overflowoutput 913 is a logical zero voltage level signal. In a certainembodiment, the predetermined state is selected such that once thesignal received at the enable/reset input 907 changes from a logicalzero voltage level signal to a logical one voltage level signal, thecounter overflow output 913 will not change to a logical one voltagelevel signal until a time equal to the time it would take, given a worstcase rapidly changing input signal, for the main filter 106 to recoverfrom a rapid change in the input signal before increasing the respectiveamplification factors of the variable gain stages of the main filter 106will not overload any of the internal nodes of the main filter 106.

[0080] A five input AND gate 902 receives the inverse of a signal from adata output 974 of the positive edge triggered D-type flip flop 972, asignal from a data output 982 of the positive edge triggered D-type flipflop 980, a signal from a data output 990 of the positive edge triggeredD-type flip flop 988, a signal from a data output 998 of the positiveedge triggered D-type flip flop 996, and a signal received from thecounter overflow output 913. The output of the AND gate 902 is connectedto one input of a two input OR gate 906. A five input AND gate 904receives a signal from the data output 974 of the positive edgetriggered D-type flip flop 972, the inverse of a signal from the dataoutput 982 of the positive edge triggered D-type flip flop 980, theinverse of a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, the inverse of a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996, and theinverse of a signal received from the counter overflow output 913. Theoutput of the AND gate 904 is connected to the other input of a twoinput OR gate 906. The output of the two input OR gate 906 is connectedto the data input 968 of the positive edge triggered D-type flip flop972.

[0081] A six input AND gate 908 receives the inverse of a signal fromthe data output 974 of the positive edge triggered D-type flip flop 972,the inverse of a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, a signal from the data output 990 of thepositive edge triggered D-type flip flop 988, the inverse of a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, the inverse of a signal received by the input 162, and a signalreceived by the input 160. The AND gate 908 provides its output to afirst input of a nine input OR gate 926. A five input AND gate 910receives the inverse of a signal from the data output 974 of thepositive edge triggered D-type flip flop 972, the inverse of a signalfrom the data output 982 of the positive edge triggered D-type flip flop980, a signal from the data output 990 of the positive edge triggeredD-type flip flop 988, a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, and a signal received by the input170. The output of the AND gate 908 is provided to a second input of thenine input OR gate 926. A five input AND gate 912 receives the inverseof a signal from the data output 974 of the positive edge triggeredD-type flip flop 972, a signal from the data output 982 of the positiveedge triggered D-type flip flop 980, the inverse of a signal from thedata output 990 of the positive edge triggered D-type flip flop 988, theinverse of a signal from the data output 998 of the positive edgetriggered D-type flip flop 996, and the inverse of a signal received bythe input 160. The output of the AND gate 914 is provided to a fourthinput of the nine input OR gate 926. A five input AND gate 914 receivesthe inverse of a signal from the data output 974 of the positive edgetriggered D-type flip flop 972, a signal from the data output 982 of thepositive edge triggered D-type flip flop 980, the inverse of a signalfrom the data output 990 of the positive edge triggered D-type flip flop988, the inverse of a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, and a signal received by the input160. The output of the AND gate 914 is provided to a fourth input of thenine input OR gate 926. A five input AND gate 916 receives the inverseof a signal from the data output 974 of the positive edge triggeredD-type flip flop 972, a signal from the data output 982 of the positiveedge triggered D-type flip flop 980, the inverse of a signal from thedata output 990 of the positive edge triggered D-type flip flop 988, asignal from the data output 998 of the positive edge triggered D-typeflip flop 996, and the inverse of a signal received from the overflowoutput 913 of the counter 911. The output of the AND gate 916 isprovided to a fifth input of the nine input OR gate 926. A five inputAND gate 918 receives the inverse of a signal from the data output 974of the positive edge triggered D-type flip flop 972, a signal from thedata output 982 of the positive edge triggered D-type flip flop 980, theinverse of a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, a signal from the data output 998 of thepositive edge triggered D-type flip flop 996, and a signal received fromthe overflow output 913 of the counter 911. The AND gate 918 is providedto a sixth input of the nine input OR gate 926. A five input AND gate920 receives the inverse of a signal from the data output 974 of thepositive edge triggered D-type flip flop 972, a signal from the dataoutput 982 of the positive edge triggered D-type flip flop 980, a signalfrom the data output 990 of the positive edge triggered D-type flip flop988, the inverse of a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, and the inverse of a signalreceived by the input 170. The output of the AND gate 920 is provided toa seventh input of the nine input OR gate 926. A five input AND gate 922receives the inverse of a signal from the data output 974 of thepositive edge triggered D-type flip flop 972, a signal from the dataoutput 982 of the positive edge triggered D-type flip flop 980, a signalfrom the data output 990 of the positive edge triggered D-type flip flop988, the inverse of a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, and a signal received by the input170. The output of the AND gate 922 is provided to an eighth input ofthe nine input OR gate 926. A five input AND gate 924 receives theinverse of a signal from the data output 974 of the positive edgetriggered D-type flip flop 972, a signal from the data output 982 of thepositive edge triggered D-type flip flop 980, a signal from the dataoutput 990 of the positive edge triggered D-type flip flop 988, a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, and the inverse of a signal received from the overflow output 913of the counter 911. The output of AND gate 924 is provided to the ninthinput of the nine input OR gate 926. The output of the nine input ORgate 926 is provided to a data input 976 of the positive edge triggeredD-type flip flop 980.

[0082] A five input AND gate 928 receives the inverse of a signal fromthe data output 974 of the positive edge triggered D-type flip flop 972,the inverse of a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, the inverse of a signal from the dataoutput 990 of the positive edge triggered D-type flip flop 988, a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, and a signal received by the input 170. The output of the AND gate928 is provided to a first input of a nine input OR gate 946. A sixinput AND gate 930 receives the inverse of a signal from the data output974 of the positive edge triggered D-type flip flop 972, the inverse ofa signal from the data output 982 of the positive edge triggered D-typeflip flop 980, a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, the inverse of a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996, theinverse of a signal received by the input 160, and the inverse of asignal received by the input 162. The output of the AND gate 930 isprovided to a second input of the nine input OR gate 946. A six inputAND gate 932 receives the inverse of a signal from the data output 974of the positive edge triggered D-type flip flop 972, the inverse of asignal from the data output 982 of the positive edge triggered D-typeflip flop 980, a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, the inverse of a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996, a signalreceived by the input 160, and the inverse of a signal received by theinput 162. The output of the AND gate 932 is provided to a third inputof the nine input OR gate 946. A six input AND gate 934 receives theinverse of a signal from the data output 974 of the positive edgetriggered D-type flip flop 972, the inverse of a signal from the dataoutput 982 of the positive edge triggered D-type flip flop 980, a signalfrom the data output 990 of the positive edge triggered D-type flip flop988, the inverse of a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, a signal received by the input 160,and the inverse of a signal received by the input 162. The output of theAND gate 934 is provided to a fourth input of the nine input OR gate946. A five input AND gate 936 receives the inverse of a signal from thedata output 974 of the positive edge triggered D-type flip flop 972, theinverse of a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, a signal from the data output 990 of thepositive edge triggered D-type flip flop 988, a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996, and theinverse of a signal received by the input 170. The output of the ANDgate 936 is provided to a fifth input of the nine input OR gate 946. Afive input AND gate 938 receives the inverse of a signal from the dataoutput 974 of the positive edge triggered D-type flip flop 972, a signalfrom the data output 982 of the positive edge triggered D-type flip flop980, the inverse of a signal from the data output 990 of the positiveedge triggered D-type flip flop 988, a signal from the data output 998of the positive edge triggered D-type flip flop 996, and a signal fromthe overflow output 913 of the counter 911. The output of the AND gate938 is provided to a sixth input of the nine input OR gate 946. A fiveinput AND gate 940 receives the inverse of a signal from the data output974 of the positive edge triggered D-type flip flop 972, a signal fromthe data output 982 of the positive edge triggered D-type flip flop 980,a signal from the data output 990 of the positive edge triggered D-typeflip flop 988, the inverse of a signal from the data output 998 of thepositive edge triggered D-type flip flop 996, and the inverse of asignal received by the input 170. The output of the AND gate 940 isprovided to a seventh input of the nine input OR gate 946. A five inputAND gate 942 receives the inverse of a signal from the data output 974of the positive edge triggered D-type flip flop 972, a signal from thedata output 982 of the positive edge triggered D-type flip flop 980, asignal from the data output 990 of the positive edge triggered D-typeflip flop 988, the inverse of a signal from the data output 998 of thepositive edge triggered D-type flip flop 996, and a signal received bythe input 170. The output of the AND gate 942 is provided to an eighthinput of the nine input OR gate 946. A five input AND gate 944 receivesthe inverse of a signal from the data output 974 of the positive edgetriggered D-type flip flop 972, a signal from the data output 982 of thepositive edge triggered D-type flip flop 980, a signal from the dataoutput 990 of the positive edge triggered D-type flip flop 988, a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, and the inverse of a signal from the overflow output 913 of thecounter 911. The output of the AND gate 944 is provided to a ninth inputof the nine input OR gate 946. The output of the nine input OR gate 946is provided to a data input 984 of the positive edge triggered D-typeflip flop 988.

[0083] A five input AND gate 948 receives the inverse of a signal fromthe data output 974 of the positive edge triggered D-type flip flop 972,the inverse of a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, the inverse of a signal from the dataoutput 990 of the positive edge triggered D-type flip flop 988, theinverse of a signal from the data output 998 of the positive edgetriggered D-type flip flop 996, and a signal received by the input 162.The output of the AND gate 948 is provided to a first input of a nineinput OR gate 966. A five input AND gate 950 receives the inverse of asignal from the data output 974 of the positive edge triggered D-typeflip flop 972, the inverse of a signal from the data output 982 of thepositive edge triggered D-type flip flop 980, the inverse of a signalfrom the data output 990 of the positive edge triggered D-type flip flop988, a signal from the data output 998 of the positive edge triggeredD-type flip flop 996, and the inverse of a signal received by the input170. The output of the AND gate 950 is provided to a second input of thenine input OR gate 966. A six input AND gate 952 receives the inverse ofa signal from the data output 974 of the positive edge triggered D-typeflip flop 972, the inverse of a signal from the data output 982 of thepositive edge triggered D-type flip flop 980, a signal from the dataoutput 990 of the positive edge triggered D-type flip flop 988, theinverse of a signal from the data output 998 of the positive edgetriggered D-type flip flop 996, a signal received by the input 162, andthe inverse of a signal received by the input 160. The output of the ANDgate 952 is provided to a third input of the nine input OR gate 966. Asix input AND gate 954 receives the inverse of a signal from the dataoutput 974 of the positive edge triggered D-type flip flop 972, theinverse of a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, a signal from the data output 990 of thepositive edge triggered D-type flip flop 988, the inverse of a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, the inverse of a signal received by the input 162, and a signalreceived by the input 160. The output of the AND gate 954 is provided toa fourth input of the nine input OR gate 966. A five input AND gate 956receives the inverse of a signal from the data output 974 of thepositive edge triggered D-type flip flop 972, the inverse of a signalfrom the data output 982 of the positive edge triggered D-type flip flop980, a signal from the data output 990 of the positive edge triggeredD-type flip flop 988, a signal from the data output 998 of the positiveedge triggered D-type flip flop 996, and the inverse of a signalreceived by the input 170. The output of the AND gate 956 is provided toa fifth input of the nine input OR gate 966. A five input AND gate 958receives the inverse of a signal from the data output 974 of thepositive edge triggered D-type flip flop 972, a signal from the dataoutput 982 of the positive edge triggered D-type flip flop 980, theinverse of a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, the inverse of a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996, and asignal received by the input 160. The output of the AND gate 958 isprovided to a sixth input of the nine input OR gate 966. A five inputAND gate 960 receives the inverse of a signal from the data output 974of the positive edge triggered D-type flip flop 972, a signal from thedata output 982 of the positive edge triggered D-type flip flop 980, theinverse of a signal from the data output 990 of the positive edgetriggered D-type flip flop 988, a signal from the data output 998 of thepositive edge triggered D-type flip flop 996, and the inverse of asignal received from the overflow output 913 of the counter 911. Theoutput of the AND gate 960 is provided to a seventh input of the nineinput OR gate 966. A five input AND gate 962 receives the inverse of asignal from the data output 974 of the positive edge triggered D-typeflip flop 972, a signal from the data output 982 of the positive edgetriggered D-type flip flop 980, a signal from the data output 990 of thepositive edge triggered D-type flip flop 988, the inverse of a signalfrom the data output 998 of the positive edge triggered D-type flip flop996, and a signal received by the input 170. The output of the AND gate962 if provided to an eighth input of the nine input OR gate 966. A fiveinput AND gate 964 receives the inverse of a signal from the data output974 of the positive edge triggered D-type flip flop 972, a signal fromthe data output 982 of the positive edge triggered D-type flip flop 980,a signal from the data output 990 of the positive edge triggered D-typeflip flop 988, a signal from the data output 998 of the positive edgetriggered D-type flip flop 996, and the inverse of a signal receivedfrom the overflow output 913 of the counter 911. The output of the ANDgate 964 is provided to a ninth input of the nine input OR gate 966. Theoutput of the nine input OR gate 966 is provided to a data input 992 ofthe positive edge triggered D-type flip flop 996.

[0084] The first D-type flip-flop 972 holds the most significant bit ofthe current state of the gain control unit 172 until the next positiveedge of the clock signal is received at the clock input 985 of the gaincontrol unit 172, at which time the most significant bit of the currentstate is provided at the data output 974 of the first D-type flip-flop972. The output 974 is coupled to a terminal 915. The second D-typeflip-flop 980 holds the second most significant bit of the current stateof the gain control unit 172 until the next positive edge of the clocksignal is received at the clock input 985 of the gain control unit 172,at which time the second most significant bit of the current state isprovided at the data output 982 of the second D-type flip-flop 980. Theoutput 982 is coupled to a terminal 917. The third D-type flip-flop 988holds the third most significant bit of the current state of the gaincontrol unit 172 until the next positive edge of the clock signal isreceived at the clock input 985 of the gain control unit 172, at whichtime the third most significant bit of the current state is provided atthe data output 990 of the third D-type flip-flop 988. The output 990 iscoupled to a terminal 919. The fourth D-type flip-flop 996 holds theleast significant bit of the current state of the gain control unit 172until the next positive edge of the clock signal is received at theclock input 985 of the gain control unit 172, at which time the leastsignificant bit of the current state is provided at the data output 998of the fourth D-type flip-flop 996. The output 998 is coupled to aterminal 921.

[0085] A four input AND gate 901 receives the inverse of a signal fromthe data output 974 of the positive edge triggered D-type flip flop 972,a signal from the data output 982 of the positive edge triggered D-typeflip flop 980, the inverse of a signal from the data output 990 of thepositive edge triggered D-type flip flop 988, and a signal from the dataoutput 998 of the positive edge triggered D-type flip flop 996. Theoutput of the AND gate 901 is provided to one input of a two input ORgate 905. A four input AND gate 903 receives the inverse of a signalfrom the data output 974 of the positive edge triggered D-type flip flop972, a signal from the data output 982 of the positive edge triggeredD-type flip flop 980, a signal from the data output 990 of the positiveedge triggered D-type flip flop 988, and a signal from the data output998 of the positive edge triggered D-type flip flop 996. The output ofthe AND gate 903 is provided to the other input of the two input OR gate905. The output of the two input OR gate 905 is provided to theenable/reset input 907 of the N-bit counter 911.

[0086] A four input AND gate 923 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, and the inverseof a signal received by the input 921. The output of the AND gate 923 isprovided to a first input of a four input OR gate 931. A seven input ANDgate 925 receives the inverse of a signal received by the input 915, theinverse of a signal received by the input 917, the inverse of a signalreceived by the input 919, a signal received by the input 921, a signalreceived by the input 166, the inverse of a signal received by the input168, and the inverse of a signal received by the input 170. The outputof the AND gate 925 is provided to a second input of the four input ORgate 931. A seven input AND gate 927 receives a signal received by theinput 915, the inverse of a signal received by the input 917, theinverse of a signal received by the input 919, the inverse of a signalreceived by the input 921, the inverse of a signal received by the input166, a signal received by the input 168, and the inverse of a signalreceived by the input 170. The output of the AND gate 927 is provided toa third input of the four input OR gate 931. A seven input AND gate 929receives a signal received by the input 915, the inverse of a signalreceived by the input 917, the inverse of a signal received by the input919, the inverse of a signal received by the input 921, the inverse of asignal received by the input 166, the inverse of a signal received bythe input 168, and a signal received by the input 170. The output of theAND gate 926 is provided to a fourth input of the four input OR gate931. The output of the four input OR gate 931 is provided to the output178.

[0087] A four input AND gate 933 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, a signal received by the input 919, and the inverse of a signalreceived by the input 921. The output of the AND gate 933 is provided toa first input of an eight input OR gate 949. A four input AND gate 935receives the inverse of a signal received by the input 915, a signalreceived by the input 917, a signal received by the input 919, and asignal received by the input 921. The output of the AND gate 935 isprovided to a second input of the eight input OR gate 949. A seven inputAND gate 937 receives the inverse of a signal received by the input 915,the inverse of a signal received by the input 917, a signal received bythe input 919, a signal received by the input 921, a signal received bythe input 166, the inverse of a signal received by the input 168, andthe inverse of a signal received by the input 170. The output of the ANDgate 937 is provided to a third input of the eight input OR gate 949. Aseven input AND gate 939 receives a signal received by the input 915,the inverse of a signal received by the input 917, the inverse of asignal received by the input 919, the inverse of a signal received bythe input 921, a signal received by the input 166, the inverse of asignal received by the input 168, and the inverse of a signal receivedby the input 170. The output of the AND gate 939 is provided to a fourthinput of the eight input OR gate 949. A seven input AND gate 941receives the inverse of a signal received by the input 915, the inverseof a signal received by the input 917, the inverse of a signal receivedby the input 919, a signal received by the input 921, the inverse of asignal received by the input 166, a signal received by the input 168,and the inverse of a signal received by the input 170. The output of theAND gate 941 is provided to a fifth input of the eight input OR gate949. A seven input AND gate 943 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, a signalreceived by the input 921, the inverse of a signal received by the input166, the inverse of a signal received by the input 168, and a signalreceived by the input 170. The output of the AND gate 943 is provided toa sixth input of the eight input OR gate 949. A seven input AND gate 945receives the inverse of a signal received by the input 915, a signalreceived by the input 917, a signal received by the input 919, theinverse of a signal received by the input 921, the inverse of a signalreceived by the input 166, a signal received by the input 168, and theinverse of a signal received by the input 170. The output of the ANDgate 945 is provided to a seventh input of the eight input OR gate 949.A seven input AND gate 947 receives the inverse of a signal received bythe input 915, a signal received by the input 917, a signal received bythe input 919, the inverse of a signal received by the input 921, theinverse of a signal received by the input 166, the inverse of a signalreceived by the input 168, and a signal received by the input 170. Theoutput of the AND gate 947 is provided to an eighth input of the eightinput OR gate 949. The output of the eight input OR gate 949 is providedto the output 180 of the gain control unit 172.

[0088] A seven input AND gate 951 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, a signalreceived by the input 921, the inverse of a signal received by the input166, a signal received by the input 168, and the inverse of a signalreceived by the input 170. The output of the AND gate 951 is provided toone input of a two input OR gate 955. A seven input AND gate 953receives the inverse of a signal received by the input 915, the inverseof a signal received by the input 917, a signal received by the input919, a signal received by the input 921, the inverse of a signalreceived by the input 166, a signal received by the input 168, and theinverse of a signal received by the input 170. The output of the ANDgate 953 is provided to the other input of the two input OR gate 955.The output of the two input OR gate 955 is provided to the output 182 ofthe gain control unit 172.

[0089] A seven input AND gate 957 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, a signalreceived by the input 921, the inverse of a signal received by the input166, a signal received by the input 168, and the inverse of a signalreceived by the input 170. The output of the AND gate 957 is provided toa first input of a four input NOR gate 965. A seven input AND gate 959receives the inverse of a signal received by the input 915, the inverseof a signal received by the input 917, a signal received by the input919, a signal received by the input 921, the inverse of a signalreceived by the input 166, a signal received by the input 168, and theinverse of a signal received by the input 170. The output of the ANDgate 959 is provided to a second input of the four input NOR gate 965. Aseven input AND gate 961 receives the inverse of a signal received bythe input 915, a signal received by the input 917, a signal received bythe input 919, the inverse of a signal received by the input 921, theinverse of a signal received by the input 166, a signal received by theinput 168, and the inverse of a signal received by the input 170. Theoutput of the AND gate 961 is provided to a third input of the fourinput NOR gate 965. A seven input AND gate 963 receives a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, the inverse of asignal received by the input 921, the inverse of a signal received bythe input 166, a signal received by the input 168, and the inverse of asignal received by the input 170. The output of the AND gate 963 isprovided to a fourth input of the four input NOR gate 965. The output ofthe four input NOR gate 965 is provided to the output 184 of the gaincontrol unit 172.

[0090] A seven input AND gate 967 receives a signal received by theinput 915, the inverse of a signal received by the input 917, theinverse of a signal received by the input 919, the inverse of a signalreceived by the input 921, the inverse of a signal received by the input166, a signal received by the input 168, and the inverse of a signalreceived by the input 170. The output of the AND gate 967 is provided toone input of a two input OR gate 971. A seven input AND gate 969receives the inverse of a signal received by the input 915, a signalreceived by the input 917, a signal received by the input 919, theinverse of a signal received by the input 921, the inverse of a signalreceived by the input 166, a signal received by the input 168, and theinverse of a signal received by the input 170. The output of the ANDgate 969 is provided to the other input of the two input OR gate 971.The output of the two input OR gate 971 is provided to the output 186 ofthe gain control unit 172.

[0091] A four input AND gate 973 receives the inverse of a signalreceived by the input 915, the inverse of a signal received by the input917, the inverse of a signal received by the input 919, and the inverseof a signal received by the input 921. The output of the AND gate 973 isprovided to a first input of a five input OR gate 983. A four input ANDgate 975 receives the inverse of a signal received by the input 915, theinverse of a signal received by the input 917, a signal received by theinput 919, and the inverse of a signal received by the input 921. Theoutput of the AND gate 975 is provided to a second input of the fiveinput OR gate 983. A four input AND gate 977 receives the inverse of asignal received by the input 915, a signal received by the input 917,the inverse of a signal received by the input 919, and the inverse of asignal received by the input 921. The output of the AND gate 977 isprovided to a third input of the five input OR gate 983. A four inputAND gate 979 receives the inverse of a signal received by the input 915,a signal received by the input 917, the inverse of a signal received bythe input 919, and a signal received by the input 921. The output of theAND gate 979 is provided to a fourth input of the five input OR gate983. A four input AND gate 981 receives the inverse of a signal receivedby the input 915, a signal received by the input 917, a signal receivedby the input 919, and a signal received by the input 921. The output ofthe AND gate 981 is provided to a fifth input of the five input OR gate983. The output of the five input OR gate 983 is provided to the output176 of the gain control unit 172.

[0092]FIG. 11 illustrates an exemplary embodiment of the transconductor742 in the peak detector 604 depicted in FIG. 7 in greater detail. Thetransconductor 742 includes an NMOS transistor Q₁, an NMOS transistorQ₂, a PMOS transistor Q₃, a PMOS transistor Q₄, an NMOS transistor Q₅,an NMOS transistor Q₆, and a current source 1124.

[0093] A signal received by the positive input 744 of the transconductor742 is applied to the gate 1105 of the NMOS transistor Q₁. The NMOStransistor Q₁ allows current to flow from its source 1107 to its drain1106, or vice versa, depending on the signal at the gate 1105 and therelative voltages at its source 1107 and at its drain 1106. The drain1106 of the NMOS transistor Q₁ is connected to the drain 1113 and thegate 1111 of the PMOS transistor Q₃, and the gate 1114 of the PMOStransistor Q₄. The source 1107 of the NMOS transistor Q₁ is connected tothe drain 1118 of the NMOS transistor Q₅ and the source 1110 of the NMOStransistor Q₂.

[0094] A signal received by the negative input 746 of the transconductor742 is applied to the gate 1108 of the NMOS transistor Q₂. The drain1109 of the NMOS transistor Q₂ is connected to the drain 1116 of thePMOS transistor Q₄ and the output 748 of the transconductor 742. Thesource 1110 of the NMOS transistor Q₂ is connected to the drain 1118 ofthe NMOS transistor Q₅, and the source 1107 of the NMOS transistor Q₁.

[0095] The drain 1113 of the PMOS transistor Q₃ is connected to thedrain 1106 of the NMOS transistor Q₁, the gate 1111 of the PMOStransistor Q₃, and the gate 1114 of the PMOS transistor Q₄. The source1112 of the PMOS transistor Q₃ is connected to supply voltage V_(dd).

[0096] The source 1115 of the PMOS transistor Q₄ is connected to supplyvoltage V_(dd).

[0097] The drain 1118 of the NMOS transistor Q₅ is connected to thesource 1107 of the NMOS transistor Q₁ and the source 1110 of the NMOStransistor Q₂. The source 1119 of the NMOS transistor Q₅ is connected tosupply voltage V_(SS). The gate 1117 of the NMOS transistor Q₅ isconnected to the gate 1120 and the drain 1121 of the NMOS transistor Q₆,and the negative terminal 1125 of the current source 1124.

[0098] The source 1122 of the NMOS transistor Q₆ is connected to supplyvoltage V_(SS).

[0099] The current source 1124 produces a bias current I_(bias) for thetransconductor 332. The bias current I_(bias) produced by the currentsource 1124 is adjusted to give a stable center frequency in thepresence of fabrication tolerances and temperature variations. The biascurrent I_(bias) can be any value, for example 100 micro-amperes, andthe transistors Q₁, Q₂, Q₃, Q₄, Q₅, Q₆ of the transconductor 742 arescaled to yield the desired transconductances. The transconductance forthe transconductors is calculated using the equation:

G _(m) =I _(tail)/(V _(GS) −V _(T)),  (3)

[0100] where I_(tail) is the current passing through the transistor Q₅,V_(T) is the threshold voltage of transistors Q₅ and Q₆, and V_(GS) isthe gate-source voltage of the transistors Q₅, Q₆. The linear range ofthe transconductor is related to the quantity V_(GS)−V_(T). Once thebias current I_(bias) has been set, the transistors Q₅, Q₆ are scaledsuch that, the following equation is satisfied:

(W _(Q5) /L _(Q5))/(W _(Q6) /L _(Q6))=I _(tail) /I _(bias),  (4)

[0101] where W_(Q5) and L_(Q5) are the width and length of the channelof NMOS transistor Q₅, respectively, and W_(Q6) and L_(Q6) are the widthand length of the channel of NMOS transistor Q₆, respectively. Thepositive terminal of the current source 1124 is connected to supplyvoltage V_(dd). The preferred form of the current source 1124 is aresistor connected to the between the supply voltage V_(dd) and thedrain 1121 and the gate 1120 of the NMOS transistor Q₆.

1. An active filter system comprising: a system input for receiving asystem input signal; a system output for providing a system outputsignal; a main filter having at least one successive filter stage havingan input and an output, including a first filter stage, each filterstage having an associated input amplification stage including a signalinput, a signal output coupled to the input of the associated filterstage and a gain control input for receiving a gain control signal thatdetermines the amplification factor of the associated inputamplification stage, the input of the input amplification stageassociated with each filter stage, except for the input amplificationstage associated with the first filter stage, being coupled to theoutput of a preceding filter stage, if any, the input of theamplification stage associated with the first filter stage being coupledto the system input, each filter stage having an associated outputamplification stage including a signal input coupled to the output ofthe associated filter stage, a signal output and a gain control inputfor receiving a gain control signal that determines the amplificationfactor of the associated output amplification stage, the signal outputof the output amplification stage associated with a selected one of theat least one filter stage being coupled to the system output; a strengthdetector having an input coupled to the output of the first filterstage, and having a first output and a second output for providingrespective output signals indicative of whether the first filter stageis approaching saturation or is providing an output signal having lessthan a minimum acceptable signal to noise ratio; a zero crossingdetector having at least one input coupled to respective ones of the atleast one output of the at least one filter stage of the main filter,and having at least one output for providing at least one signalindicative of when a successive one of the at least one filter stage ofthe main filter provides a signal at its output that is approximatelyequal to zero; and a gain control unit having a first input and a secondinput respectively coupled to the output of the strength detector andcoupled to the at least one output of the zero crossing detector, andhaving a multiplicity of outputs for providing respective gain controlsignals to the gain control input of each input amplification stage andeach output amplification stage associated with the at least one filterstage of the main filter, the gain control unit being responsive tosignals provided initially by the strength detector indicative of thefirst filter stage approaching saturation or providing an output signalhaving less than the minimum acceptable signal to noise ratio, and asignal from the zero crossing detector indicative of the output signalprovided by the first filter stage being approximately equal to zero forproviding a gain control signal to the gain control input of the inputamplification stage associated with the first filter stage so that theinput amplification stage associated with the first filter stage has anamplification factor that results in a signal strength at its signaloutput which avoids saturation of the first filter stage and avoids thefirst filter stage providing a signal having less than the minimumacceptable signal to noise ratio, and for providing a gain controlsignal to the gain control input of the output amplification stageassociated with the first filter stage so that the output amplificationstage associated with the first filter stage has an amplification factorwhich is the reciprocal of the amplification factor of the inputamplification stage associated with the first filter stage, the gaincontrol unit being thereafter responsive to signals provided initiallyby the strength detector indicative of the first filter stage of themain filter approaching saturation or providing an output having lessthan the minimum acceptable signal to noise ratio, and to a signal fromthe zero crossing detector indicating that an output signal at theoutput of a successive filter stage, if any, being approximately equalto zero for providing a gain control signal to the gain control input ofthe input amplification stage associated with the successive filterstage so that the input amplification stage associated with thesuccessive filter stage has an amplification factor that results in asignal strength at its signal output that avoids saturation of thesuccessive filter stage and avoids the successive filter stage providinga signal having less than the minimum acceptable signal to noise ratio,and for providing a gain control signal to the gain control input of theoutput amplification stage associated with the successive filter stageso that the output amplification stage associated with the successivefilter stage has an amplification factor which is a reciprocal of theamplification factor of the input amplification stage associated withthe successive filter stage.
 2. An active filter system according toclaim 1, wherein the at least one filter stage of the main filtercomprises a first filter stage and a second filter stage, and the zerocrossing detector comprising: a switching unit having a first signalinput coupled to the output of the first filter stage, a second signalinput coupled to the output of the second filter stage, a switch controlinput, and a signal output, the switching unit being responsive to afirst switch control signal received by the switch control terminal forconnecting the first signal input to the signal output and disconnectingthe second signal input from the signal output, and being responsive toa second switch control signal received by the switch control terminalfor connecting the second signal input to the signal output anddisconnecting the first signal input from the signal output; acomparator having a signal input coupled to the signal output of theswitching unit, and a signal output for providing an output signal, thecomparator providing a first logical signal on the signal output if thesignal received at the signal input is approximately equal to zero, andproviding a second logical signal on the signal output if the signalreceived at the signal input is not approximately equal to zero; and athree-stage shift register having a clock input coupled to the signaloutput of the comparator, a reset/enable input, a first stage output, asecond stage output and a third stage output, the shift register beingresponsive to a first logical signal received at the reset/enable inputfor producing a first logical signal at the first stage output, a secondlogical signal at the second stage output and a second logical signal atthe third stage output, and being responsive to receiving the secondlogical signal at the reset/enable input and a signal changing from thesecond logical signal to the first logical signal at the clock inputwhile having the first logical signal at the first stage output, thesecond logical signal at the second stage output and the second logicalsignal at the third stage output for providing the second logical signalat the first stage output, the first logical signal at the second stageoutput and the second logical signal at the third stage output, theshift register being responsive to the first logical signal received atthe reset/enable input and a signal changing from the second logicalsignal to the first logical signal at the clock input while having thesecond logical signal at the first stage output, the first logicalsignal at the second stage output and the second logical signal at thethird stage output for providing the second logical signal at the firststage output, the second logical signal at the second stage output andthe first logical signal at the third stage output, and being responsiveto the first logical signal received at the reset/enable input and asignal changing from the second logical signal to the first logicalsignal at the clock input while having the second logical signal at thefirst stage output, the second logical signal at the second stage outputand the first logical signal at the third stage output for providing thesecond logical signal at the first stage output, the second logicalsignal at the second stage output and the first logical signal at thethird stage output, and wherein the first stage output, the second stageoutput and the third stage output are the output signals of the zerocrossing detector provided to the gain control unit, and the first stageoutput is also the switch control terminal of the switching unit.
 3. Theactive filter system of claim 2, wherein the gain control unit has afirst zero cross input coupled to the first stage output of the shiftregister and the switch control input of the switching unit, a secondzero cross input coupled to the second stage output of the shiftregister, a third zero cross input coupled to the third stage output ofthe shift register, a reset/enable output for providing a reset/enablesignal to the reset/enable input of the shift register, a first gaincontrol output terminal, a second gain control output terminal, a thirdgain control output terminal, a fourth gain control output terminal anda fifth gain control output terminal; the gain control unit beingresponsive to receiving a first signal from the strength detectorindicative of the first filter stage providing a signal having less thanthe minimum acceptable signal to noise ratio when the first gain controlterminal is providing a second logical signal, the second gain controlterminal is providing the second logical signal, the third gain controlterminal is providing the second logical signal, the fourth gain controlterminal is providing a first logical signal and the fifth gain controlterminal is providing the second logical signal, for providing thesecond logical signal on the reset/enable output, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the first logical signal on the second zero cross input andthe second logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the second logicalsignal on the first gain control output terminal, the first logicalsignal on the second gain control output terminal, the second logicalsignal on the third gain control output terminal, the second logicalsignal on the fourth gain control output terminal and the first logicalsignal on the fifth gain control output terminal, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the second logical signal on the second zero cross inputand the first logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the first logicalsignal on the first gain control output terminal, the second logicalsignal on the second gain control output terminal, the second logicalsignal on the third gain control output terminal, the first logicalsignal on the fourth gain control output terminal and the second logicalsignal on the fifth gain control output terminal; the gain control unitbeing responsive to receiving a signal from the signal strength detectorindicative of the first filter stage providing a signal having less thanthe minimum acceptable signal to noise ratio while the first gaincontrol output terminal is providing the first logical signal, thesecond gain control output terminal is providing the second logicalsignal, the third gain control output terminal is providing the secondlogical signal, the fourth gain control output terminal is providing thefirst logical signal and the fifth gain control output is providing thesecond logical signal, for providing after a particular time delay thesecond logical signal on the reset/enable output, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the first logical signal on the second zero cross input andthe second logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the second logicalsignal on the first gain control output terminal, the first logicalsignal on the second gain control output terminal, the first logicalsignal on the third gain control output terminal, the second logicalsignal on the fourth gain control output terminal and the second logicalsignal on the fifth gain control output terminal, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the second logical signal on the second zero cross inputand the first logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the second logicalsignal on the first gain control output terminal, the first logicalterminal on the second gain control output terminal, the second logicalsignal on the third gain control output terminal, the first logicalsignal on the fourth gain control output terminal and the second logicalsignal on the fifth gain control output terminal; the gain control unitbeing responsive to receiving a signal from the strength detectorindicative of the first filter stage approaching saturation while thefirst gain control output is providing the second logical signal, thesecond gain control output is providing the first logical signal, thethird gain control output terminal is providing the second logicalsignal, the fourth gain control output is providing the second logicalsignal and the fifth gain control output terminal is providing thesecond logical signal, for providing after a particular time delay thesecond logical signal on the reset/enable output, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the first logical signal on the second zero cross input andthe second logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the second logicalsignal on the first gain control output terminal, the second logicalsignal on the second gain control output terminal, the first logicalsignal on the third gain control output terminal, the second logicalsignal on the fourth gain control output terminal and the second logicalsignal on the fifth gain control output terminal, and being thereafterresponsive to receiving the second logical signal on the first zerocross input, the second logical signal on the second zero cross inputand the first logical signal on the third zero cross input for providingthe second logical signal on the reset/enable output, the second logicalsignal on the first gain control output terminal, the second logicalsignal on the second gain control output terminal, the second logicalsignal on the third gain control output terminal, the first logicalsignal on the fourth gain control output terminal and the second logicalsignal on the fifth gain control output terminal, and wherein: the gaincontrol input of the input amplification stage associated with the firstfilter stage comprises a first gain control terminal and a second graincontrol terminal, the first gain control terminal of the inputamplification stage associated with the first filter stage of the mainfilter being coupled to the first gain control output terminal of thegain control unit, and the second gain control terminal of the inputamplification stage associated with the first filter stage of the mainfilter is coupled to the second gain control output terminal of the gaincontrol unit, the input amplification stage associated with the firstfilter stage being responsive to receiving the second logical signal onits first gain control terminal and the second logical signal on itssecond gain control terminal for amplifying the input signal by a firstamplification factor, and being responsive to receiving the secondlogical signal on the first gain control terminal and the first logicalsignal on the second gain control terminal for amplifying the inputsignal by a second amplification factor which is greater than the firstamplification factor, and being responsive to receiving the firstlogical signal on the first gain control terminal and the second logicalsignal on the second gain control terminal for amplifying the inputsignal by a third amplification factor which is greater than the secondamplification factor; the gain control input of the output amplificationstage associated with the first filter stage comprises a first gaincontrol terminal and a second gain control terminal, the first gaincontrol terminal of the output amplification stage associated with thefirst filter stage being coupled to the first gain control outputterminal of the gain control unit, the second gain control terminal ofthe output amplification stage associated with the first filter stage iscoupled to the second gain control output terminal of the gain controlunit, the output amplification stage associated with the first filterstage being responsive to receiving the second logical signal on itsfirst gain control terminal and the second logical signal on its secondgain control terminal for amplifying a signal provided by the output ofthe first filter stage by the third amplification factor, and beingresponsive to receiving the second logical signal on its first gaincontrol terminal and the first logical signal on its second gain controlterminal for amplifying the signal provided by the output of the firstfilter stage by the second amplification factor, and being responsive toreceiving the first logical signal on the first gain control terminaland the second logical signal on the second gain control terminal foramplifying the signal provided by the output of the first filter stageby the first amplification factor; the gain control input of the inputamplification stage associated with the second filter stage comprises athird grain control terminal and a fourth gain control terminal, thethird gain control terminal of the input amplification stage associatedwith the second filter stage being coupled to the third gain controloutput terminal of the gain control unit, and the fourth gain controlterminal of the input amplification stage associated with the secondfilter stage is coupled to the fourth gain control output terminal ofthe gain control unit, the input amplification stage associated with thesecond filter stage being responsive to receiving the first logicalsignal on its third gain control terminal and the second logical signalon its fourth gain control terminal for amplifying a signal provided bythe output of the first filter stage by a fourth amplification factor,and being responsive to receiving the second logical signal on its thirdgain control terminal and the first logical signal on its fourth gaincontrol terminal for amplifying the signal provided by the output of thefirst filter stage by a fifth amplification factor which is greater thanthe fourth amplification factor, and being responsive to receiving thefirst logical signal on its third gain control terminal and the secondlogical signal on its fourth gain control terminal for amplifying thesignal provided by the output of the first filter stage by a sixthamplification factor which is greater than the fifth amplificationfactor; and the gain control input of the output amplification stageassociated with the second filter stage comprises a fourth gain controlterminal and a fifth gain control terminal, the fourth gain controlterminal of the output amplification stage associated with the secondfilter stage being coupled to the fourth gain control output terminal ofthe gain control unit, the fifth gain control terminal of theamplification stage associated with the second filter stage beingcoupled to the fifth gain control unit, the output amplification stageassociated with the second filter stage being responsive to receivingthe second logical signal on its fourth gain control terminal and thesecond logical signal on its fifth gain control terminal for amplifyinga signal provided by the output of the second filter stage by the fourthamplification factor, and being responsive to receiving the secondlogical signal on its fourth gain control terminal and the first logicalsignal on its fifth gain control terminal for amplifying the signalprovided by the output of the second filter stage by the sixthamplification factor, and being responsive to receiving the firstlogical signal on its fourth gain control terminal and the secondlogical signal on its fifth gain control terminal for amplifying thesignal provided by the output of the second filter stage by the fifthamplification factor.
 4. The active filter system of claim 3, whereinthe signal strength detector comprises: a peak detector having an inputcoupled to the output of the first filter stage of the main filter andan output, the peak detector detecting a voltage envelope peak of thesignal provided by the output of the first filter stage and providing asignal representative of the voltage envelope peak at its output; afirst threshold detector having an input coupled to the output of thepeak detector and an output, the first threshold detector comparing thesignal provided by the peak detector with a first thresholdrepresentative of a signal strength at the input of the first filterstage that would cause the first filter stage to approach saturation,the first threshold detector providing the first logical signal at itsoutput if the signal received from the peak detector is less than thefirst threshold, and providing the second logical signal at its outputif the signal received from the peak detector is greater than or equalto the first threshold; and a second threshold detector having an inputcoupled to the output of the peak detector and an output, the secondthreshold detector comparing the signal from the peak detector with asecond threshold representative of an input signal strength at the inputof the first filter stage that would cause a signal provided by theoutput of the first filter to have less than a minimum acceptable signalto noise ratio, the second threshold detector providing the firstlogical signal at its output if the signal from the peak detector isgreater than or equal to the second threshold, and for providing thesecond logical signal at its output if the signal from the peak detectoris less than the second threshold, wherein the output of the firstthreshold detector and the output of the second threshold detectorcomprise the first and second outputs of the strength detector,respectively.
 5. The active filter system of claim 3, wherein the firstfilter stage comprises a first integrator having an input and an output,and the second filter stage comprises a second integrator having aninput and an output.
 6. The active filter system of claim 2, wherein theinput of the output amplification stage associated with the secondfilter stage is coupled to the output of the second filter stage, andthe output of the output amplification stage associated with the secondfilter stage is coupled to the signal input of the input amplificationstage associated with the second filter stage, and wherein the signaloutput of the output amplification stage associated with the firstfilter stage is coupled to the system output.
 7. The active filtersystem of claim 2, wherein the input amplification stage associated withthe first filter stage includes circuitry for clamping an output signalprovided by the input amplification stage so as to prevent saturation ofthe first filter stage.
 8. The active filter system of claim 2, whereinthe input amplification stage associated with the second filter stageincludes circuitry for clamping an output signal provided by the inputamplification stage so as to prevent saturation of the second filterstage.
 9. The active filter system of claim 6, wherein the outputamplification stage associated with the second filter stage includescircuitry for clamping an output signal provided by the outputamplification stage so as to prevent saturation of the second filterstage.
 10. An active filter system according to claim 5, wherein theinput amplification stage associated with the first filter stageincludes: a first resistor; a second resistor; a third resistor; afourth resistor; a capacitor; a first switch having a first terminal, asecond terminal and a switch control terminal; a second switch having afirst terminal, a second terminal and a switch control terminal; and anoperational amplifier having an inverted input, a normal input and anoutput, the first resistor being connected between the system input andthe inverting input of the operational amplifier, the second resistorbeing connected between the system input and the first terminal of thefirst switch, the third resistor being connected between the systeminput and the first terminal of the second switch, the second terminalof the first switch being coupled to the inverting input of theoperational amplifier, the second terminal of the second switch beingcoupled to the inverting input of the operational amplifier, the fourthresistor being coupled between the output and the inverting input of theoperational amplifier, the capacitor being coupled between the outputand the inverting input of the operational amplifier, the normal inputof the operational amplifier being coupled to ground, the switch controlterminal of the first switch being coupled to the second gain controlterminal, the switch control terminal of the second switch being coupledto the first gain control terminal, wherein each of the first switch andthe second switch is responsive to receiving the first logical signal onits switch control terminal for connecting its first terminal to itssecond terminal, and is responsive to receiving the second logicalsignal on its switch control terminal for disconnecting its firstterminal from its second terminal.
 11. The active filter system of claim10, wherein the first resistor has a resistance of 200 kΩ, the secondresistor has a resistance of 22.22 kΩ, the third resistor has aresistance of 2.02 kΩ has a resistance of 20 kΩ, and the capacitor 80pF.
 12. The active filter system of claim 5, wherein the firstintegrator comprises: a resistor; a capacitor; and an operationalamplifier having an inverting input, a normal input and an output, theresistor being coupled between the output and the inverting input of theoperational amplifier, the capacitor being coupled between the outputand the inverting input of the operational amplifier, the normal inputof the operational amplifier being coupled to ground, the invertinginput of the operational amplifier being coupled to the input of thefirst integrator, and the output of the operational amplifier beingcoupled to the output of the first integrator.
 13. The active filtersystem of claim 12, wherein the resistor has a resistance of 20 kΩ andthe capacitor has a capacitance of 80 pF.
 14. The active filter systemof claim 5, wherein the output amplification stage associated with thefirst filter stage comprises: a first resistor; a second resistor; athird resistor; a fourth resistor; a first switch having a firstterminal, a second terminal and a switch control terminal; a secondswitch having a first terminal, a second terminal and a switch controlterminal; and an operational amplifier having a normal input, aninverting input and an output, the first resistor being coupled betweenthe output of the first integrator and the inverting input of theoperational amplifier, the second resistor being coupled between theoutput and the inverting input of the operational amplifier, the thirdresistor being coupled between the inverting input of the operationalamplifier and the first terminal of the first switch, the fourthresistor being coupled between the inverting input of the operationalamplifier and the first terminal of the second switch, the secondterminal of the first switch being coupled to the output of theoperational amplifier, the second terminal of the second switch beingcoupled to the output of the operational amplifier, the normal input ofthe operational amplifier being coupled to ground, the switch controlterminal of the first switch being coupled to the second gain controlinput terminal and the switch control terminal of the second switchbeing coupled to the first gain control terminal, wherein each of thefirst switch and the second switch is responsive to receiving the firstlogical signal on its switch control terminal for connecting its firstterminal to its second terminal, and is responsive to receiving thesecond logical signal on its switch control terminal for disconnectingits first terminal from its second terminal.
 15. The active filtersystem according to claim 14, wherein the first resistor has aresistance of 20 kΩ, the second resistor has a resistance of 200 kΩ, thethird resistor has a resistance of 22.22 kΩ and the fourth resistor hasa resistance of 2.02 kΩ.
 16. The active filter system of claim 5,wherein the input amplifier stage associated with the second filterstage comprises: a first resistor; a second resistor; a third resistor;a capacitor; a first switch having a first terminal, a second terminaland a switch control terminal; a second switch having a first terminal,a second terminal and a switch control terminal; and an operationalamplifier having a normal input, an inverting input and an output, thefirst resistor being coupled between the output of the first integratorand the inverting input of the operational amplifier, the secondresistor being coupled between the output of the first integrator andthe first terminal of the first switch, the third resistor being coupledbetween the output of the first integrator and the first input of thesecond switch, the second terminal of the first switch being coupled tothe inverting input of the operational amplifier, the second terminal ofthe second switch being coupled to the inverting input of theoperational amplifier, the capacitor being coupled between the outputand the inverting input of the operational amplifier, the normal inputof the operational amplifier being coupled to ground, the switch controlterminal of the first switch being coupled to the fourth gain controlterminal and the switch control terminal of the second switch beingcoupled to the third gain control terminal, wherein each of the firstswitch and the second switch is responsive to receiving a first logicalsignal on its switch control terminal for connecting its first terminalto its second terminal, and is responsive to receiving the secondlogical signal on its switch control terminal for disconnecting itsfirst terminal from its second terminal.
 17. The active filter system ofclaim 16, wherein the first resistor has a resistance of 10 kΩ, thesecond resistor has a resistance of 1.01 kΩ, the third resistor has aresistance of 0.10 kΩ and the capacitor has a capacitance of 80 pF. 18.The active filter system of claim 5, wherein the second integratorcomprises a capacitor, and an operational amplifier having a normalinput, an inverting input and an output, the capacitor being coupledbetween the output and the inverting input of the operational amplifier,the inverting input of the operational amplifier being coupled to theinput of the second integrator, the output of the operational amplifierbeing coupled to the output of the second integrator, the normal inputof the operational amplifier being coupled to ground.
 19. The activefilter system of claim 6, wherein the output amplification stageassociated with the second filter stage comprises: a first resistor; asecond resistor; a third resistor; a fourth resistor; a fifth resistor;a sixth resistor; a capacitor; a first switch having a first terminal, asecond terminal and a switch control terminal; a second switch having afirst terminal, a second terminal and a switch control terminal; a firstoperational amplifier having a normal input, an inverting input and anoutput; and a second operational amplifier having a normal input, aninverting input and an output, the first resistor being coupled betweenthe output of the second integrator and the inverting input of the firstoperational amplifier, the second resistor being coupled between theoutput and the inverting input of the first operational amplifier, thethird resistor being coupled between the output of the first operationalamplifier and the inverting input of the second operational amplifier,the fourth resistor being coupled between the inverting input of thesecond operational amplifier and the first terminal of the first switch,the fifth resistor being coupled between the inverting input of thesecond operational amplifier and the first terminal of the secondswitch, the second terminal of the first switch being coupled to theoutput of the first operational amplifier, the second terminal of thesecond switch being coupled to the output of the first operationalamplifier, the normal output of the first operational amplifier beingcoupled to ground, the sixth resistor being coupled between the outputand the inverting input of the second operational amplifier, thecapacitor being coupled between the output and the inverting input ofthe second operational amplifier and the normal input of the secondoperational amplifier being coupled to ground, wherein each of the firstswitch and the second switch is responsive to receiving the firstlogical signal on its switch control terminal for connecting its firstterminal to its second terminal, and is responsive to receiving thesecond logical signal on its switch control terminal for disconnectingits first terminal from its second terminal.
 20. The active filtersystem of claim 19, wherein the first resistor has a resistance of 10kΩ, the second resistor has a resistance of 10 kΩ, the third resistorhas a resistance of 10 kΩ, the fourth resistor has a resistance of 1.11kΩ, the fifth resistor has a resistance of 0.10 kΩ, the sixth resistorhas a resistance of 20 kΩ, and the capacitor has a capacitance of 80 pF.21. The active filter system of claim 4, wherein the gain control unitcomprises a multiple state logic circuit responsive to the signalsprovided by the first and second threshold detectors of the strengthdetector, and the signals received at the first zero cross input, thesecond zero cross input and the third zero cross input for derivingrespective signals on the first gain control output terminal, the secondgain control output terminal, the third gain control output terminal,the fourth gain control output terminal and the fifth gain controloutput terminal.